Estimating phase-locked loop jitter due to substrate coupling: a cyclostationary approach

Chan, H.H.Y.; Žilić, Željko

doi:10.1109/isqed.2004.1283691

SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)

DOI: 10.1109/isqed.2004.1283691

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Estimating phase-locked loop jitter due to substrate coupling: a cyclostationary approach

H.H.Y. Chan

Željko Žilić

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Cited by 2 publications

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“…However, limited attempts have been made to develop a PLL model that deals with the PTV effect of the noise injected into the PLL loop. In [22], [23], cyclostationary approaches to PLL jitter analysis due to substrate noise coupling are presented. The investigation is mainly about substrate noise coupling through the VCO and limited theoretical analysis is presented.…”

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confidence: 99%

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Vamvakos

Stojanović

Nikolić

2011

IEEE Trans. Circuits Syst. I

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Abstract-Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.

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mentioning

confidence: 99%

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Vamvakos

Stojanović

Nikolić

2011

IEEE Trans. Circuits Syst. I

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Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

et al. 2006

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Estimating phase-locked loop jitter due to substrate coupling: a cyclostationary approach

Cited by 2 publications

References 12 publications

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

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