Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Afzali-Kusha, Ali; Nagata, Makoto; Verghese, Nishath K.; Allstot, D.J.

doi:10.1109/jproc.2006.886029

Cited by 106 publications

(29 citation statements)

References 118 publications

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“…The impedance between the ring and ground pad is modeled by Z gnd . Finally, the substrate resistance between the ring and victim is represented by R sub which is determined by (1) and (2).…”

Section: B Guard Ring Isolationmentioning

confidence: 99%

“…Substrate noise coupling continues to be a primary concern in highly heterogeneous mixed-signal circuits such as transceivers where digital and analog/RF functions are placed on the same monolithic substrate [1]. The demand for higher integration exacerbates this issue due to the reduced physical distance between the aggressor digital and sensitive analog/RF blocks.…”

Section: Introductionmentioning

confidence: 99%

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Compact substrate models for efficient noise coupling and signal isolation analysis

Jakushokas

Salman

Friedman

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract-Current propagation within a lightly doped substrate is approximated with a half-ellipse to efficiently estimate substrate resistances. As opposed to existing work, the proposed model contains only one fitting parameter. Compact models are also developed to determine the isolation efficiency of several commonly used structures such as a guard ring and triple well. The accuracy of these models is verified by comparing the models with a commercial substrate extraction tool based on a boundary element method. These models are used to compare several isolation structures within an industrial mixed-signal circuit with a lightly doped substrate.

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Section: B Guard Ring Isolationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compact substrate models for efficient noise coupling and signal isolation analysis

Jakushokas

Salman

Friedman

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…[9] The previous simulation result in fig. 6, has been calculated by (1), After all, it is unable to show the effect of the power/ground noise on the noise figure.…”

Section: Where K=boltzman's Constant T0 = 290kmentioning

confidence: 99%

Noise Figure Degradation Analysis of Power/Ground Noise on 900MHz LNA for UHF RFID

Koo

Park

Shim

et al. 2007

2007 9th Electronics Packaging Technology Conference

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“…Such an environment imposes extremely difficult working conditions for the analogue filters due to the presence of a high level, broadband noise generated by the digital sub-circuits. The digital noise, which propagates along a silicon substrate, can significantly degrade the dynamic range of the analogue filters [3,4]. One of the most commonly used method to reduce the substrate noise interference is based on application of the fully-differential filters, capable of reducing the influence of the common-mode (CM) component of the noise.…”

Section: Introductionmentioning

confidence: 99%

Technique to improve CMRR at high frequencies in CMOS OTA-C filters

Blakiewicz¹

2013

Bulletin of the Polish Academy of Sciences: Technical Sciences

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Abstract. In this paper a technique to improve the common-mode rejection ratio (CMRR) at high frequencies in the OTA-C filters is proposed. The technique is applicable to most OTA-C filters using CMOS operational transconductance amplifiers (OTA) based on differential pairs. The presented analysis shows that a significant broadening of CMRR bandwidth can be achieved by using a differential pair with the bodies of transistors connected to AC ground, instead of using a pair with the bodies connected to the sources. The key advantages of the technique are: no increase in power consumption (except for an optional tuning circuit), a small increase of a chip area, a slight modification of the original filter. The simulation results for exemplary OTAs and a low-pass filter, designed in a 0.35 µm CMOS process, show the possibility of broadening the CMRR bandwidth several times.

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Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Cited by 106 publications

References 118 publications

Compact substrate models for efficient noise coupling and signal isolation analysis

Compact substrate models for efficient noise coupling and signal isolation analysis

Noise Figure Degradation Analysis of Power/Ground Noise on 900MHz LNA for UHF RFID

Technique to improve CMRR at high frequencies in CMOS OTA-C filters

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