Dynamically Reconfigurable Architectures for Software-Defined Radio in Professional Electronic Applications

Rousseau, Bruno; Manet, Philippe; Delavallée, Thibault; Loiselle, Igor; Legat, Jean-Didier

doi:10.1007/978-94-007-1125-9_20

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…Prior to the advent of 5G communications, the growing interest in SDR and cognitive radio led to research efforts towards flexible and reconfigurable baseband processors. Apart from the trade-offs between GPU flexibility and ASIC performance, the possibility for DPR in SRAM-based FPGAs makes them compelling hardware platforms for baseband architectures for agile and flexible radio communications [11][12][13]. Early works exploited DPR for the design of specific modules in the baseband processing chain, like FIR filters or constellation mappers [14,15].…”

Section: Background and Related Workmentioning

confidence: 99%

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Ferreira

2018

Electronics

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The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.waveforms (FBMC, UFMC, GFDM) intermingled with a variety of 3G and 4G waveforms" [3]. In heavily used portions of the spectrum, such as the sub-6 GHz band, multi-waveform coexistence requires Dynamic Spectrum Access (DSA) and Carrier Aggregation (CA) techniques to achieve a more efficient spectrum utilization [1].Other important factors in 5G NR are cost minimization and energy efficiency. Cloud Radio Access Networks (C-RANs) attempt to achieve a more efficient energy consumption and resource allocation by deploying a central Baseband processing Unit (BBU) that serves multiple Remote Radio Heads (RRHs) [4]. This network architecture relies on reconfigurable hardware modules to implement BBUs supporting the different access technologies and modes of operation used by RRHs.The realization of the 5G vision will strongly rely on the design of hardware infrastructure adjusted to the challenges imposed by future wireless communications. Regarding digital baseband processing, hardware designs should be: (1)flexible to support multiple services requirements, waveforms, and numerologies; (2) evolvable/forward-compatible to be easily upgradeable with new functionalities and future modes of operation, thus extending the system's duty lifetime; (3) energy-efficient and (4) cost-effective. FPGAs are convenient platforms to design systems with these characteristics. Apart from their capacity for parallel intensive computation, FPGAs feature a high degree of flexibility not only at design time, but also at runtime, through Dynamic Partial Reconfiguration (DPR) [5]: the ability to reconfigure portions of FPGA logic fabric (reconfigurable regions) while the other portions remain unchanged and running. This increases the FPGA functional density, as mutually-exclusive circuits/functionalities are implemented o...

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Section: Background and Related Workmentioning

confidence: 99%

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Ferreira

2018

Electronics

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Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Farisi

Heyse

Bruneel

et al. 2014

Des Autom Embed Syst

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Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 % of the routing configuration static and therefore reduce the routing reconfiguration time by 50 %, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 %

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Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator

Ferreira

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Dynamically Reconfigurable Architectures for Software-Defined Radio in Professional Electronic Applications

Cited by 4 publications

References 14 publications

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator

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