Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

ACM Trans. Reconfigurable Technol. Syst.

Huang

Shen

et al. 2010

Self Cite

With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime task relocation. In this work, we propose a new Relocatable Hardware-Software Scheduling (RHSS) method that not only can be applied to dynamically relocatable hardware-software tasks, but also increases the reconfigurable hardware resource utilization, reduces the reconfigurable hardware resource fragmentation with realistic placement methods, and makes best efforts at meeting the real-time constraints of tasks. The feasibility of the proposed relocatable hardware-software scheduling algorithm was proved by applying it to some randomly generated examples and a real dynamically reconfigurable network security system example. Compared to the quadratic time complexity of the state-of-the-art Adaptive Hardware-Software Allocation (AHSA) method, RHSS is linear in time complexity, and improves the reconfigurable hardware utilization by as much as 117.8%. The scheduling and placement time and the memory usage are also drastically reduced by as much as 89.5% and 96.4%, respectively. -C. 2010. Scheduling and placement of hardware/software real-time relocatable tasks in dynamically partially reconfigurable systems.

Section: Dprs System Modelmentioning

confidence: 99%

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

ACM Trans. Reconfigurable Technol. Syst.

Huang

Shen

et al. 2010

Self Cite

“…Another alternative is to use the proposed hardware preemption wrappers [18,19] for enhancing hardware functions with the capability of dynamic swapping. Thus, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems to increase the utilization of hardware space per unit time.…”

Section: Configuration Layermentioning

confidence: 99%

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Huang

Journal of Systems Architecture

Shen

2010

Self Cite

To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UMLbased hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS can not only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also * Corresponding author: Tel.: Preprint submitted to Journal of Systems Architecture August 13, 2010 determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.

“…Comparing configurations (3), (4), (5), we observe that configuration (3) has the worst performance because the functions are executed sequentially, in a single chain. Compared to configuration (5) and all other configurations, configuration (4) gives the best performance. This is because the most time consuming chain such as DES here is given the highest priority in RMS.…”

Section: Performance Modelmentioning

confidence: 99%

“…Given the large amount of resources, Dynamically Partially Reconfigurable Systems (DPRS) can now be implemented in a single FPGA [5]. Unlike von-Neumann based architectures, there are currently no standard memory hierarchy and communication schemes for DPRS.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures

Shih

Hung

2007 International Conference on Field-Programmable Technology

2007

Self Cite

Dynamically reconfigurable systems either adopt a processor-controlled networked architecture or a sequencer-controlled data flow architecture. In the networked architecture, the processor is overloaded with data transfer requests, whereas in the data flow architecture, the burden is completely shiftedfrom the processor to the data sequencer As a tradeoff between these two extremes, this work proposes a novel module sequencer architecture, which not only allows the processor and the sequencer to share the heavy data communication load, but is also more coherent with the conventional processor-FPGA architecture. Further, the architecture is highly flexible because it can be tuned to fit a particular application. Application examples show how the proposed architecture is superior to the networked architecture in terms of lower communication load and to the data flow architecture in terms ofreduced system complexity.