Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

Hsiung, Pao-Ann; Huang, Chun-Hsian; Shen, Jih-Sheng; Chiang, Chen-Chi

doi:10.1145/1857927.1857936

Cited by 13 publications

(12 citation statements)

References 20 publications

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“…In the future, to maintain a DPRS infrastructure to support the design of self-adaptable systems [30], our previously proposed relocatable hardwaresoftware scheduling (RHSS) method [15] will be further extended and integrated in the hardware task manager. Thus, system performance can be selfoptimized to adapt to changing environment conditions and runtime user requirements.…”

Section: Discussionmentioning

confidence: 99%

“…In our current implementation, the hardware task manager adopts a sim-ple First-In-First-Out (FIFO) method for scheduling hardware tasks. To efficiently use the hardware virtualization and preemption mechanisms to adapt changing environment conditions and runtime user requirements, in the future, the previously proposed Relocatable Hardware-Software Scheduling (RHSS) method [15] will be further extended and integrated in the hardware task manager.…”

Section: Management Layermentioning

confidence: 99%

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Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Huang

Hsiung

Shen

2010

Journal of Systems Architecture

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To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UMLbased hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS can not only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also * Corresponding author: Tel.: Preprint submitted to Journal of Systems Architecture August 13, 2010 determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.

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Section: Discussionmentioning

confidence: 99%

Section: Management Layermentioning

confidence: 99%

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Huang

Hsiung

Shen

2010

Journal of Systems Architecture

Self Cite

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“…The authors of [JTY + 99] describe a dynamically reconfigurable system that can support multiple applications running concurrently and implement a strategy to preload FPGA configurations in order to reduce the execution time. The authors of [HHSC10] propose a scheduling algorithm that can cope with dynamically relocating tasks from software to hardware, or vice versa. The authors of [PSA10] propose reconfiguration strategies for minimizing the number of reconfigurations.…”

Section: Dynamic Configuration Prefetchingmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...

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“…Furthermore, the scheme of [10] neither incorporates partial reconfiguration nor placement optimization. The selection algorithm discussed in [19] incorporates partial reconfiguration, but this work does not account for multiple IVs per hardware accelerator. The scheme of [20] discusses a 'selection' algorithm which accounts for multiple IVs, but this work does not allow for partial reconfiguration and lack placement optimization.…”

Section: Coprocessor-based Techniquesmentioning

confidence: 99%

ISOMER: Integrated selection, partitioning, and placement methodology for reconfigurable architectures

Bilal

Hafiz

Shafique

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Quality system design on dynamic partially reconfigurable platform needs exploration of a vast and multidimensional design space for (1) selection among implementation variants of hardware accelerators, (2) partitioning the reconfigurable fabric, and (3) their placement on the reconfigurable fabric partitions. This paper presents a novel methodology ISOMER for integrated solution of selection, partitioning and placement for performance optimization. Architecture under consideration is a general purpose processor coupled with reconfigurable fabric that can be partitioned in multi-sized partially reconfigurable bins. Our methodology determines performance-efficient partitioning and usage of reconfigurable fabric. Extensive evaluation illustrates that our methodology is scalable and outperforms state-of-the-art techniques for non-partially reconfigurable architectures.

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Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

Cited by 13 publications

References 20 publications

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

ISOMER: Integrated selection, partitioning, and placement methodology for reconfigurable architectures

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