ISOMER: Integrated selection, partitioning, and placement methodology for reconfigurable architectures

Abstract

Quality system design on dynamic partially reconfigurable platform needs exploration of a vast and multidimensional design space for (1) selection among implementation variants of hardware accelerators, (2) partitioning the reconfigurable fabric, and (3) their placement on the reconfigurable fabric partitions. This paper presents a novel methodology ISOMER for integrated solution of selection, partitioning and placement for performance optimization. Architecture under consideration is a general purpose processor coupled with reconfigurable fabric that can be partitioned in multi-sized partially reconfigurable bins. Our methodology determines performance-efficient partitioning and usage of reconfigurable fabric. Extensive evaluation illustrates that our methodology is scalable and outperforms state-of-the-art techniques for non-partially reconfigurable architectures.

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

“…Between 15% and 40% of the nodes were selected as hardware candidates (those with the highest software execution times), and their hardware execution time was generated β times smaller than their software one (the coefficient β models the hardware speedups). We considered two possible situations: in the first one, β was chosen from the uniform distribution on [10 3 , 3 · 10 3 ] (fast hardware: applications exhibiting high hardware acceleration), in order to reflect the results obtained from our board measurements (see Section VI-A); in the second situation, we generated much lower speedups, from the uniform distribution on [3,7] (slow hardware: applications exhibiting lower hardware acceleration), similar to the assumptions from [32]. We also generated the size of the candidates in concordance with our real-life implementation of the SUSAN image processing algorithm.…”

“…The reconfiguration time for the modules was determined based on their size, considering the average throughput of our DMA reconfiguration controller (375 MB/s). The placement was decided using existing techniques (like [9] or [3]) that minimize the number of placement conflicts. We generated problem instances where the size of the reconfigurable region is a fraction (15% or 25%) of the total area required by all candidates, MAX HW = m∈H area(m).…”

“…The software execution times were obtained considering the following cycles per instruction (CPI) values: for calls, returns and floating point instructions CPI = 3, for load, store and branch instructions CPI = 2, and for other instructions CPI = 1. Similar to the previous experimental sections, we considered the hardware execution time β times smaller than the software one, where β was chosen from the uniform distribution on the interval [10 3 , 3 · 10 3 ] to simulate a fast hardware implementation and from [3,7] to simulate a slow hardware implementation.…”

An Investigation Into Partitioning Algorithms for Automatic Heterogeneous Compilers

“…These tools [8] use parsers [11] (shown in Figure 2) to read in a given software language [12], followed by partitioning algorithms to choose which pieces of the original software go into a hardware partition. After this a compiler (or compilers) automatically create the necessary interfaces between hardware/software crossover points and convert the partitions into software code and a hardware description language (HDL).…”

“…This can come in the form of a Field Programmable Gate Array (FPGA) [6] combined with a processor. This enables a common software interface [7], such as a command line interface (CLI) or graphical user interface (GUI), to combine [8] with accelerating hardware such as an FPGA. Interfaces exist between the two domains, usually in the form of queues or shared memory.…”