xUAVs: Towards Efficient Approximate Computing for UAVs—Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization

Abstract

High Definition (HD) image processing and real-time analytics over live video feeds have always been the key requirements for Intelligence, Surveillance and Reconnaissance (ISR) applications. With the evolution of optics and image enhancement techniques, computational loads of HD ISR systems are also rising exponentially. On the contrary, the slowdown of Moore's Law has recently posed challenging bounds over the level of achievable miniaturization for emerging processing and storage units. FPGAs provide higher computational density for ISR applications while allowing lower Size, Weight, and Power (SWaP) profiles for aerial platforms such as Unmanned Aerial Vehicles (UAVs). A promising solution to bridge this gap between resource-constrained host platforms and computation-intensive FPGA applications is the paradigm of Approximate Computing. It compromises on the accuracy of processed results to offer significant performance gains for errortolerant applications, such as video and image processing. In this paper, we present a novel approximate adder design methodology, for FPGA-based systems with improved SWaP performance, besides preserving the accuracy requirements within acceptable thresholds. The design methodology proposed in this paper focuses on the FPGA-specific Look-Up Table (LUT) architecture to introduce approximations while splitting the carry chain into LUT-based sub-adders, with flexible overlap to tune the adder's accuracy and achieve the overall latency of a single LUT. The paper presents several variants of the proposed design and offers applicationoriented flexibility to adjust for optimal SWaP vs accuracy trade-off. We have further devised a comprehensive assessment approach to verify functional viability of the proposed atomic arithmetic blocks at system level, through their implementation into dense computational imaging applications, such as 2-dimensional Discrete Cosine Transform (DCT), airborne self-localization and moving object tracking algorithms, in comparison with other state-of-the-art adders. Our most accurate design performs at least 9.9% better in power consumption when compared with existing approximate adders, which proves that the proposed methodology holds promising potential to improve SWaPindex for computation-intensive UAV applications. INDEX TERMS Aerial ISR applications, Approximate Adders, Approximate Computing, FPGA, Moving object tracking, Self-localization I. INTRODUCTION High-resolution aerial imaging and automated yet actionable video analytics are widely-being deployed by military and other government-sponsored law enforcement agencies for on-demand Intelligence, Surveillance and Reconnaissance (ISR) operations, autonomous Combat,

Low Error Efficient Approximate Adders for FPGAs

“…High speed segmented approximate adders (xUAV) for FPGAs are proposed in [23]. Segmentation is done in 2, 3, or 5-bit groups for efficient mapping to LUTs.…”

“…In this section, we compare the proposed approximate adders with segmented and speculative adders in the literature; Almost Correct Adder (ACA-I) [9], Accuracy Configurable Adder (ACA-II) [11], Block-based Carry Speculative Adder (BCSA) [24], Error-tolerant adder II (ETA-II) [10], and xUAV [23].…”

“…xUAV is an FPGA-specific segmented adder. Several configurations of xUAV are proposed in [23]. We used two most efficient configurations; one with the lowest error (m = 5, r = 1) and the other with low error and low area (m = 3, r = 1).…”

“…The efficiency of FPGA-based implementations of these applications can be improved through approximate computing. Only a few FPGA specific approximate adders have been proposed in the literature [19]- [23]. These approximate adders focus on improving either the efficiency or accuracy.…”

SCPA: A Segemented Carry Prediction Approximate Adder Structure

“…It can be used for multimedia and image processing, digital signal process-ing, wireless communication, data mining, and other errorresilient applications to achieve more energy reduction and performance improvement at the cost of acceptable accuracy loss [2]. Various kind of approximate computational techniques have been proposed at different software/hardware levels, and many approximate adder designs solving system performance bottlenecks have been proposed [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], which are mostly through hardware manipulation, logic simplification, and voltage overscaling to achieve energy and speed gains [19]. The design idea of approximate computation can greatly reduce the delay and circuit area of addition computation and significantly improve the performance.…”