Dynamics of high-frequency CMOS dividers

Singh, Ullas; Green, M.

doi:10.1109/iscas.2002.1010730

Cited by 61 publications

(33 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…5. The maximum operating frequency of 10.1 GHz is obtained at a supply voltage of 2 V. With the same supply voltage, the tuning range is 5.2 GHz and is in good agreement with the values predicted by (3). When the supply voltage decreases to 1.2 V, the divider realizes a lower power consumption while maintaining a moderate operating frequency in the 3.5-to 7-GHz range.…”

Section: A Core Divider Performancesupporting

confidence: 84%

“…This process compensation submodule is only operational during one-time factory calibration and has no influence on the power consumption of the proposed divider during normal operation. It should be noted that the reference divider chain should employ robust, high-speed static dividers such as the CML-based dividers in [3]. These dividers occupy minimal area when compared with LC-based dividers, and their high power usage can be tolerated since they are not powered during normal operation.…”

Section: Process-compensation Architecturementioning

confidence: 99%

“…Current mode logic (CML) flip- flop-based frequency dividers described in [3] and [4] generally achieve a high speed of operation. However, CML latches require constant biasing and therefore consume power even when there are no clock inputs.…”

mentioning

confidence: 99%

See 2 more Smart Citations

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

Weste

Parameswaran

2007

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

Section: A Core Divider Performancesupporting

confidence: 84%

Section: Process-compensation Architecturementioning

confidence: 99%

See 1 more Smart Citation

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

Weste

Parameswaran

2007

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…All modules of the divider are CML style. DFF is realized by two CML latches, which operate in master-slave manner [7,8]. "Master1" and "slave1" latches constitute the DFF1, with "master2" and "slave2" the DFF2.…”

Section: Circuit Designmentioning

confidence: 99%

0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

Chen

Guo

Lai

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

An ultra-wideband differential divide-by-1.5 divider based on current-mode logic (CML) is proposed. It consists of a divide-by-3 circuit and an optimized CML-XOR gate. Fully symmetric and differential structure is proposed to extend upper bound working frequency. In the CML-XOR gate, two identical Gilbert cells with optimized eight-input signals are developed to strengthen the pull-down force, which benefits the high-speed division. Fabricated in TSMC 180 nm CMOS process, this divider achieves an operating frequency of 0.3-4.4 GHz for 0 dBm input, and consumes 4.14 mW from 1.8 V supply. The chip size is 0.02 mm 2 .

show abstract

“…The analysis of dynamics of the static MCML prescalers has been presented by Singh and Green [3]. The self-oscillation phenomenon gives a deeper understanding of the operational principle.…”

Section: Introductionmentioning

confidence: 99%

A current-shaping technique for static MOS current-mode logic prescalers

Shi

Taishan

et al. 2013

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:This letter presents a current-shaping technique for static MOS current-mode logic (MCML) prescalers. Simply with two extra current-shaping capacitors the self-oscillating frequecy is increased. A current vector model is also presented to illustrate the principles. The prescaler with the current-shaping technique was fabricated in a 0.18-μm CMOS technology with a reference classic one. The measurement results show that the self-oscillating frequency of the prescaler with current-shaping achieves an improvement of 10%, resulting a 6 GHz highest operating frequency while the classic one could only work at 5.3 GHz. Consequently, the current-shaping technique improves the maxim divide range of the prescaler with 13.2%. Keywords: current-mode logic, prescaler, current-shaping Classification: Integrated circuits References[1] M. Alioto, R. Mita, and G. Plumbo, "Design of high-speed power-efficient MOS current-mode logic frequency dividers," IEEE Trans. Circuits Syst.

show abstract

Dynamics of high-frequency CMOS dividers

Cited by 61 publications

References 3 publications

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

A current-shaping technique for static MOS current-mode logic prescalers

Contact Info

Product

Resources

About