Early wire characterization for predictable network-on-chip global interconnects

Hatirnaz, I.; Badel, Stéphane; Pazos, Nuria; Leblebici, Yusuf; Murali, Srinivasan; Atienza, David; DeMicheli, Giovanni

doi:10.1145/1231956.1231969

Cited by 10 publications

(3 citation statements)

References 26 publications

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“…Unfortunately, as technology scales to the nanometer regime, topology analysis and exploration needs to be performed with novel methodologies and tools that account for the effects of nanoscale physics, largely impacting final performance and even feasibility of many NoC topologies. A general guideline driving network-on-chip (NoC) design under severe technology constraints consists of silicon-aware decision-making at each hierarchical level [18]. This is likely to result in less design re-spins and in faster timing closure.…”

Section: Related Workmentioning

confidence: 99%

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Ludovici

Gaydadjiev

Gilabert

et al. 2010

Proceedings of the Third International Workshop on Network on Chip Architectures

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Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone to bridge this gap, in fact, we propose a comprehensive analysis framework to assess k-ary n-mesh and C-mesh topologies at different level of abstractions, from system to layout level, while capturing implications of system and layout parameters across design hierarchy. When a certain topology proves to be slow due to long links crossing the chip, pipeline stages have been inserted to cope with such slow-down. Furthermore, costs of such speed-up technique have been evaluated to draw a comprehensive performance/area figure.The gap between the constraints driving the design of onchip vs. off-chip interconnection networks (and hence the gap between the final network architectures selected for use in each domain) is increasingly widening even more as an effect of the relentless pace of technology scaling to the nanoscale regime. New physical effects come into play and may either degrade performance/power in an unpredictable way or even affect feasibility of the design at hand or of specific architecture design techniques.Examples concern the large buffering cost associated with techniques borrowed from the off-chip domain (e.g., for congestion management strategies or for deadlock-free and multicast friendly switching mechanisms) which are not affordable in the on-chip domain. Moreover, the interconnect reverse scaling is making designs for on-chip integration increasingly interconnect-dominated, due to the delay associated with the shrinking cross-section area of on-chip interconnects. This effect becomes increasingly severe at each technology node and tends to widen the gap between post-synthesis and postplace&route performance figures and even to move critical path delays from logic blocks to large global wires.Selection of the topology connectivity pattern in the early stages of network design is a decision which is extremely sensitive to both the effects illustrated above. In fact, topologies for on-chip networks must match the 2D silicon surface, while off-chip realizations are dictated by board/rack organization. The 2D mapping constraint raises implementation issues such as wire crossings, wires of uneven length or the decrease of switch operating frequency with the number of I/O ports. As an ultimate consequence, topologies borrowed from off-chip networks should be reassessed in the on-chip environment and validated against...

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Section: Related Workmentioning

confidence: 99%

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Ludovici

Gaydadjiev

Gilabert

et al. 2010

Proceedings of the Third International Workshop on Network on Chip Architectures

View full text Add to dashboard Cite

show abstract

“…A general guideline driving network-on-chip (NoC) design under severe technology constraints consists of silicon-aware decision-making at each hierarchical level [21]. This is likely to result in less design re-spins and in faster timing closure.…”

Section: Introductionmentioning

confidence: 99%

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Gilabert

Ludovici

Medardoni

et al. 2009

2009 International Conference on Complex, Intelligent and Software Intensive Systems

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Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at different levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility of representative k-ary n-mesh topologies and by providing silicon-aware system-level performance figures

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“…The way these issues are addressed in the early design phases not only results in more or less efficient NoC designs, but can even limit their practical feasibility. As a general guideline, driving NoC designs under severe technology constraints consists of making silicon-aware decisions at each hierarchical level of the design flow [54]. This is likely going to result in less design re-spins and in faster timing closure.…”

Section: Network On-chip Modellingmentioning

confidence: 99%

Design Space Exploration for Networks On-chip

Villamón¹

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Early wire characterization for predictable network-on-chip global interconnects

Cited by 10 publications

References 26 publications

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Design Space Exploration for Networks On-chip

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