Security features such as privacy and device authentication are required in wireless sensor networks, electronic IDs, Radio Frequency Identification tags, and many other applications. These features are provided using cryptography. Symmetric key cryptography, where the key is distributed between the communication parties prior to communication, does not provide adequate solution for large scalable systems such as sensor networks. In these cases, public-key cryptography should be used. However, public-key algorithms are typically more computationally intensive than their symmetric key counterparts, which creates difficulties in meeting the strict area, power, and energy requirements. Elliptic curve cryptography, because of relatively small operand sizes, can be used to answer the imposed challenges. In this paper, we present a processor for elliptic curve cryptography over GF (2 163 ). This processor can perform elliptic curve point multiplication as well as general modular operations. The processor is flexible enough to support multiple cryptographic protocols. The chip is fabricated using UMC .13 m 1P8M process, resulting in a core area of 0.54 mm 2 . The energy consumption to perform one elliptic curve point multiplication is 5.1 J. The design features lightweight countermeasures against side-channel attacks. A security evaluation shows the effectiveness of such countermeasures.The ECC processor presented in[1] uses a 16 × 16 bit multiplier and a 1 Kb random-access memory (RAM) to achieve small area. However, this approach resulted in a large execution time of 251 clock cycles for a field multiplication and 296K clock cycles per PM. The design presented in[2] uses a latch based memory unit and a digit-serial data path to achieve lower execution time. Neither of these two implementations can support the basic Schnorr protocol[3] as they lack instructions for modular arithmetic operations.In this paper, we present a processor for ECC based on the architecture presented by Lee et al.[4] We make the following extensions of the previous work:• The register file was modified to reduce the number of multiplexers. • Bit-sliced architecture of the register file and the modular arithmetic logic unit (MALU) was developed. An efficient placement and routing strategy was used to minimize the interconnect capacitive loads. ‡ Area and power associated with the interconnect are not included in this analysis. Frequency values are chosen in such way that the time needed to execute the complete protocol is less than 250 ms.