Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC

Shim, Minseob; Jeong, Seokhyeon; Myers, Paul; Bang, Suyoung; Shen, Junhua; Kim, Chulwoo; Sylvester, Dennis; Blaauw, David; Jung, Wanyeong

doi:10.1109/jssc.2016.2631299

Cited by 64 publications

(29 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The second modification performed to reduce the dynamic power consumption of the OC circuit was done by utilizing a current starved inverter which is proposed in [40]. This inverter was modified by adding one p-type transistor at the top and one n-type transistor at the bottom of the regular inverter circuit, as shown in Fig.…”

Section: Oscillator Collapse (Oc)mentioning

confidence: 99%

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

et al. 2021

View full text Add to dashboard Cite

The main purpose of this paper is to achieve ultra-low power Physical Unclonable Function (PUF) to meet the requirements for Internet of Things (IoT) applications. PUFs are promising hardware security primitives that are based on the uniqueness and the unclonability of the device's physical characteristics to provide a unique identifier for devices. PUFs can be used in device authentication and for secure key storage and generation. This paper presents Oscillator Collapse Physical Unclonable Function (OC-PUF), which is suitable for low power applications. The power consumption is reduced based on designing the most power-hungry modules in the OC-PUF. An Oscillator Collapse (OC) is designed to work in the near-threshold voltage region, which reduces the power consumption. More power reduction is achieved by designing a new Collapse Time Comparator (CTC). Due to the process variations, the oscillations period of each OC is different. The CTC generates the output response bit by comparing the oscillations periods of the two selected OCs. The simulation results demonstrate that the proposed OC-PUF can effectively reduce the power consumption. The proposed PUF is designed using 20 nm triple gate FinFET technology. The Simulation results for 1000 different chips with the same input challenge, show that the average power is 140 nW, with the worst case being 740 nW. The best case is 63 nW per challenge-response pair at supply voltage 0.5 V. The averaged reliability of the OC-PUF is 99.8%, at temperatures from-40 to 125 • C and supply voltage 0.5 ± 10%. The proposed OC-PUF decreases the power consumption while retaining high-performance metrics. INDEX TERMS Authentication, hardware security, low power consumption, process variation, reliability, transient effect of ring oscillator.

show abstract

Section: Oscillator Collapse (Oc)mentioning

confidence: 99%

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

et al. 2021

View full text Add to dashboard Cite

show abstract

“…Comparators are omnipresent building blocks in mixed-signal systems. Applications such as memories [1][2][3], data receivers [4][5][6], and Analog-to-Digital Converters (ADCs) [7][8][9] necessitate high speed, low noise/offset, yet power-and area-efficient designs. Their role in ADCs (Successive Approximation Register (SAR), flash, pipeline) ( Figure 1) is of special importance, since they need to accurately translate small analog signals into digital information.…”

Section: Introductionmentioning

confidence: 99%

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

View full text Add to dashboard Cite

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

show abstract

“…Then accounting for process scaling the area of the state machine should be 4.672 mm 2 × (40/130) 2 = 0.442 mm 2 . This gives a total area of 0.146 mm 2 + 0.442 mm 2 = 0.588 mm 2 , which is still almost twice the area reported in [20].…”

Section: Advantages With Process Scalingmentioning

confidence: 65%

“…The method of using a binary-weighted charge redistribution capacitor array is still widely used today. Recent publications using the idea or variations of it include [7], [8], [9], and [20]. [7] and [9] use a binary-weighted array for the LSBs, but use a thermometer-coded array for the MSBs in order to avoid problems associated…”

Section: Binary-weighted Sar Adcmentioning

confidence: 99%

See 1 more Smart Citation

Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC

Berton¹

View full text Add to dashboard Cite

A 10-bit successive approximation register (SAR) analog to digital converter (ADC) was designed in a 130 nm CMOS process. The reference voltage generator in the ADC is made with an array of 25 unit capacitors, in comparison to binary-weighted SAR ADCs, which would use 1024 unit capacitors. The capacitor array is controlled using a state machine whose logic was determined and automatically generated using a recursive backtracking algorithm. Schematic-level simulation results for the ADC predict an effective number of bits (ENOB) of 9.39, worst case integral non-linearity (INL) and differential non-linearity (DNL) of 1.15 and 1 least significant bit (LSB), respectively, and average power consumption of 1.65 µW at 10 kSps. The Walden figure of merit is calculated to be 246 fJ/conv-step. The core layout area is 0.458 mm 2 .

show abstract

Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC

Cited by 64 publications

References 18 publications

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC

Contact Info

Product

Resources

About