EFCAD — An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation

Abstract

This paper combines a chain of academic tools to form an FPGA compilation flow for building partially reconfigurable modules on lightweight embedded platforms. Our flow -EFCAD -supports the entire stack from RTL (Verilog) to (partial) bitstream, and we demonstrate early results from the onchip ARM processor of, and targeting, the latest 16nm generation of a Xilinx UltraScale+ FPGA-SoC device. With this, we complement Xilinx's PYNQ initiative to not only facilitate System-on-Chip research and education entirely within an embedded system, but also to allow building new and specialising existing customcomputing accelerators without needing access to a workstation.

A Self-Compilation Flow Demo on FOS – The FPGA Operating System

“…Starting to use FPGA systems is a non-trivial task as users may need to learn one of the hardware description languages (HDLs) as well as to download, install, maintain, and operate complex FPGA toolchains. With the introductions of the Pynq initiative [1] and an academic self-compilation EFCAD flow [2], there is a solution to build lightweight selfcontained and out-of-the-box FPGA systems for educational purposes. Everything that is needed to run an FPGA hardware programming labs consists of a small FPGA board fitted with a mico-SD card (installed with FOS and EFCAD).…”