Effect of Application Mapping on Network-on-Chip Performance

Çelik, Coşkun; Bazlamaçcı, Cüneyt F.

doi:10.1109/pdp.2012.48

Cited by 12 publications

(3 citation statements)

References 15 publications

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“…However, NoC applications usually possess traffic patterns that are not directly mapped to Poisson distributions [11]. More precisely, Poisson model fails to capture important network characteristics such as self-similarity or long-range dependence [12]. Some approaches, like [13] circumvent these limitations using a traffic approach based on a non-stationary and multifractal analysis.…”

Section: Introductionmentioning

confidence: 99%

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net

Silveira¹,

Cadore²,

Barroso³

et al. 2020

JICS

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Network-on-Chip (NoC) is a power architecture that emerged to solve communication issues present in modern Systems-on-Chip (SoCs). NoC based architectures are very scalable and offer high levels of communication parallelism, among other features. Every efficient NoC implementation requires several design steps to accomplish indices of performance. Although there are many system level models, high-level models for NoC are representative in the context of design since they provide fast and accurate analysis, with low modeling effort, for further VHDL implementations. This work proposes a NoC model based on a Timed Colored Petri Net (TCPN) that computes performance indices seamlessly. Network latency and buffer occupation are of special interest in our approach as they represent the key indices when assessing NoC performance. As results, we have validated and refined the model of a 5×5 mesh NoC comparing its indices with equivalent VHDL RTL description under synthetic and real traffic situations. The proposed model is capable of analyzing the influence of the router service time on the average latency time, enabling internal NoC evaluation to optimize buffer length. Simulation results demonstrate the model suitability for latency evaluation with time estimation errors often below 1%. Furthermore, this paper discusses the effort required to extend the model with other NoC architectural features. We conclude that the use of a TCPN model of NoC generates accurate results providing as much detailed information as their equivalent experiments using VHDL description.

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Section: Introductionmentioning

confidence: 99%

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net

Silveira¹,

Cadore²,

Barroso³

et al. 2020

JICS

View full text Add to dashboard Cite

show abstract

“…Such NoC uses the different routing algorithms and flow control technique to overcome the networking problem faced in previous on chip network architecture. Such problems render the chance for doing on chip network performance optimization [1]; due to the more packets on the network traffic merge [2] is also one of the challenges. The NoC router provides high speed and cost effective network.…”

Section: Introductionmentioning

confidence: 99%

Performance enhancement and area optimization of 3×3 NoC using random arbiter

S¹,

Jatti²,

Batra³

2015

2015 IEEE International Advance Computing Conference (IACC)

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Network-on-Chip (NoC) is a new approach for designing the communication subsystem among IP cores in aSystem-on-Chip (SoC). NoC applies networking theory and related methods to on-chip communication and brings out notable improvements over conventional bus and crossbar interconnections. NoC offers a great improvement over the issues like scalability, productivity, power efficiency and signal integrity challenges of complex SoC design. In a NoC, the communication among different nodes is achieved by routing packets through a pre-designed network according to different routing algorithms. Therefore, architecture and related routing algorithm plays an important role to the improvement of overall performance of a NoC. The technique one which is used presently in node is priority based technique packet routing which leads the packet stacking which intern leads to performance degradation. In this paper, proposes a modified random Arbiter combined with deterministic XY routing algorithm to be used on router of NoC. In this method router contains random arbiter along with priority encoder which results into fast way to transfer packet via a specific path between the nodes of the network without stacking. This in turn optimizes the packet storage area and avoids collision because node arbiter will service the packets randomly without any priority. In addition to that this method will ensure a packet always reaches the destination through the possible shortest path without deadlock and livelock.

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“…NoC design flow contains many problems from different areas, for example networking, embedded design and computer architecture [1]. Application mapping is one of the most important dimensions in NoC research.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement in Multiprocessors using Two Row Boundary Allocation Method and Online Dynamic Compaction Algorithm

Reza¹,

Rafie²

2015

IJCA

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In this paper, two row boundary (TRB) allocation algorithm and limited top-down compaction (LT-DC) migration method are proposed. The first scheme, attempts to allocate the free nodes in the center of the mesh and decrease the problem of external fragmentation. The next mechanism use task migration to improve the performance of existing sub-mesh allocation strategies. It should be noted that in this process three key metrics are considered. They are average execution time, average response time, and average wait time. In fact, we perform rigorous simulation experiments based on practical workloads as reported in the literature to quantify all our proposed schemes and compare them against standard schemes existing in the literature. Based on the results, we make clear recommendations on the choice of the strategies. General TermsNetwork on Chip

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Effect of Application Mapping on Network-on-Chip Performance

Cited by 12 publications

References 15 publications

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net

Performance enhancement and area optimization of 3×3 NoC using random arbiter

Performance Improvement in Multiprocessors using Two Row Boundary Allocation Method and Online Dynamic Compaction Algorithm

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Effect of Application Mapping on Network-on-Chip Performance

Cited by 12 publications

References 15 publications

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net

Performance enhancement and area optimization of 3&#x00D7;3 NoC using random arbiter

Performance Improvement in Multiprocessors using Two Row Boundary Allocation Method and Online Dynamic Compaction Algorithm

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Performance enhancement and area optimization of 3×3 NoC using random arbiter