Effect of ash process on leakage mechanism of Cu/ELK (k=2.5) interconnect for 65/45 nm generation

Electrical Breakdown in Advanced Interconnect Dielectrics

“…Second, the material must not suffer any significant degradation in its fundamental properties (chemical/physical/materials, thermal, and electrical properties) during process and integration [127,[138][139][140][141][142][143]. Unfortunately, dielectric degradation during certain process steps is a major concern for both LKs (major concern) and porous ULKs (much greater concern) because they are susceptible to damage during the ashing process (in particular, O 2 -based plasmas) to remove photoresist residues [152][153][154][155][156][157][158][159][160][161]. Unfortunately, dielectric degradation during certain process steps is a major concern for both LKs (major concern) and porous ULKs (much greater concern) because they are susceptible to damage during the ashing process (in particular, O 2 -based plasmas) to remove photoresist residues [152][153][154][155][156][157][158][159][160][161].…”

Near-Field Scanning Microwave Microscope for Interline Capacitance Characterization of Nanoelectronics Interconnect

“…This allows for a test vehicle with capacitance on the order of 1 fF, and therefore significantly reduced size as compared to typical interdigital capacitors. For comparison, state of the art capacitance sensitivity of less than a zepto-Farad has been demonstrate 2 (5) d (5) we relate C LL to the probe resonant equency as follows d in scanning capacitance microscopy at several GHz [23].…”

“…where C t is the net near-field probe tip capacitance, and (2FZ 0 ) -1 = 1.25 pF is the resonator capacitance. For a typical frequency measurement sensitivity of 1 kHz (5) shows that the microscope's sensitivity to C t is about 0.3 aF. This allows for a test vehicle with capacitance on the order of 1 fF, and therefore significantly reduced size as compared to typical interdigital capacitors.…”

“…To overcome the effect of parasitic capacitances associated with the pads and LCR leads the comb capacitance has to be greater than a few pico-Farads, which requires the structures to be larger than 100 × 100 μm in size. The comb accuracy is typically limited to 10 to 50 % due to stray fields, fringing effects, and statistical pattern variation across the comb [1,5]. Usually multiple interdigital capacitors are patterned onto the wafer to address a wide range of interline spacings and/or line widths.…”