Effect of Chiral Vector on Voltage Transfer Characteristics of CNTFET Inverter

Paul, Anisha; Pradhan, Buddhadev

doi:10.1109/iccece48148.2020.9223027

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…Despite notable advancements in silicon semiconductor technology, CNFETs have the capability to emerge as robust contenders, offering reliability, high performance, and low power consumption. Due to their appropriate carrier mobility and symmetrical [1] and balanced subthreshold electrical performance, carbon nanotube field-effect transistors (CNFETs) are being viewed as a possible future option for AI devices that demand low power consumption and high throughput [2][3][4]. These CNFET graphene sheets are rolled into single-walled carbon nanotubes (CNTs), and the graphene sheets can be either metal or semiconductor depending on the direction in which they are rolled.…”

Section: Introductionmentioning

confidence: 99%

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

Kim,

Alnatsheh,

Yadav

et al. 2024

Electronics

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As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

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Section: Introductionmentioning

confidence: 99%

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

Kim,

Alnatsheh,

Yadav

et al. 2024

Electronics

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“…The immense growth of semiconductor industries in last few years has prompted the semiconductor device technology to achieve higher performance of integrated circuits while implementing in smaller area and thus has entered nano meter regime through continuous scaling down activity. Unavoidable limitations and issues faced by CMOS technology in nano dimensions have encouraged the researchers to explore some alternatives [1,2].…”

Section: Introductionmentioning

confidence: 99%

CNTFET-based design of ternary logic gates with interchangeable standard positive and negative ternary output

Paul

Pradhan

2021

Eng. Res. Express

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This paper presents a novel CNTFET based design of ternary logics gates where all three ternary logics including standard, positive and negative ternary logic (ST, PT and NT) outputs for each gate are obtained from one structure and are interchangeable through some control inputs. Ternary logic overpowers the conventional binary logic in simplicity and energy efficiency as it reduces number of interconnects and chip area. In this paper design of ternary inverter, buffer, NAND, AND, NOR, OR, XOR and XNOR gates are presented where a unique feature of conversion between ST, PT, NT logic through a single output is being introduced. Besides a single logic gate is designed for a particular logic function and its complement combining both ternary and binary logic gate design technique. The proposed designs utilize the unique property of CNTFET, such as assigning the required threshold voltage value of the FET by changing the diameter of the carbon nanotube (CNT) through its chiral vector values which is very useful in designing multiple-valued logic (here ternary logic). The proposed circuits are simulated using Synopsys HSPICE with 32 nm CNTFET model provided by Stanford University and in each case average power values and propagation delays are duly noted. The effects of variation in some process parameters like channel length, dielectric oxide thickness and number of carbon nanotubes also have been discussed.

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Energy-Efficient CNTFET-RRAM Based Ternary Logic Design

Haq,

Sharma

2023

2023 3rd International Conference on Advancement in Electronics &Amp; Communication Engineering (AECE)

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Effect of Chiral Vector on Voltage Transfer Characteristics of CNTFET Inverter

Cited by 5 publications

References 10 publications

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

CNTFET-based design of ternary logic gates with interchangeable standard positive and negative ternary output

Energy-Efficient CNTFET-RRAM Based Ternary Logic Design

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