Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device

Abstract

Here, we developed the optimal conditions in terms of physical and electrical characteristics of the barrier and tungsten (W) deposition process of a contact module, which is the segment connecting the device and the multi-layer metallization (MLM) metal line in the development of 100 nm-class logic devices. To confirm its applicability to the logic contact of barrier and W films, a contact hole was formed, first to check the bottom coverage and the filling status of each film, then to check the electrical resistance and leakage characteristics to analyze the optimal conditions. At an aspect ratio of 3.89:1, ionized metal plasma (IMP) Ti had a bottom coverage of 40.9% and chemical vapor deposition (CVD) titanium nitride (TiN) of 76.2%, confirming that it was possible to apply the process to 100 nm logic contacts. W filling was confirmed, and a salicide etching rate (using Radio Frequency (RF) etch) of 13–18 Å/s at a 3.53:1 aspect ratio was applied. The etching rate on the thermal oxide plate was 9 Å/s. As the RF etch amount increased from 50–100 Å, the P active resistance increased by 0.5–1 Ω. The resistance also increased as the amount of IMP Ti deposition increased to 300 Å. A measurement of the borderless contact junction leakage current indicated that the current in the P + N well increased by more than an order of magnitude when IMP Ti 250 Å or more was deposited. The contact resistance value was 0.5 Ω. An AC bias improved the IMP Ti deposition rate by 10% in bottom coverage, but there was no significant difference in contact resistance. In the case of applying IMP TiN, the overall contact resistance decreased to 2 Ω compared to CVD TiN, but the distribution characteristics were poor. The best results were obtained under the conditions of RF etch 50 Å, IMP Ti 200 Å, and CVD TiN 2 × 50 Å.

Editorial for the Special Issue on the ICAE 2019

“…In this Special Issue, 10 technical papers are published on piezoelectric devices [ 1 , 2 , 3 , 4 ], biomedical devices [ 5 , 6 ], micromachining [ 7 , 8 ], and complementary metal-oxide-semiconductor (CMOS) logic devices [ 9 , 10 ]. For the piezoelectric devices, high-density piezoelectric micromachined ultrasonic transducer array based on patterned aluminum nitride thin film is introduced for imaging application [ 1 ].…”

“…Finally, the effect of the deposition conditions for contact resistance in a multilevel CMOS logic interconnect device and process optimization through multilevel plug inter-connections in CMOS logic devices are discussed [ 9 , 10 ]. In the first paper, the authors present the optimal conditions in terms of the physical and electrical properties of the barrier and tungsten deposition process of a contact module, which is the segment that contains the device and the multi-layer metallization (MLM) metal line in the development of 100 nm-class CMOS logic devices [ 9 ]. In the second paper, they report on optimizing the device and wiring in a via structure applied to MLM used in CMOS logic devices [ 10 ].…”