“…The subthreshold slope = / ( ) is 4 / and 1.5 / , for the p-type and n-type transistor, respectively. The different results from a different trap density at the WSe /dielectric interface, implying a higher trap density when the WSe channel is covered by PMMA, which adds a second interface [43,44]. The trap states manifest also as a hysteresis in the transfer curve, as shown in the inset of Figure 2 (b), due to trapping and detrapping of charge carriers, whose potential adds to that of the back-gate [41,42,45,46].…”