Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis

Gautam, Rajni; Saxena, Manoj; Gupta, Rashmi; Gupta, Mridula

doi:10.1016/j.microrel.2011.12.014

Cited by 50 publications

(22 citation statements)

References 30 publications

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“…IIP 3 serves as the input power at which first and third order harmonic powers are equal. VIP 2 , VIP 3 and IIP 3 should be as high as possible for better RF and analog performances [11]. A summary of the obtained results is given in Table 1.…”

Section: Resultsmentioning

confidence: 95%

“…In addition, higher transconductance derivatives can lead to intermodulation for RF-applications. To evaluate the immunity of both devices under study, we extract the values of g m1 , g m2 and g m3 at a fixed value of I ds ¼ 0.3 mA (R s can be computed using the surface potential profile for both structures), then we compute the following metrics [11] characteristics from dc analysis. VIP 2 represents the input voltage at which the first and second harmonic voltages are equal.…”

Section: Resultsmentioning

confidence: 99%

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Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

Bentrcia

Djeffal

Chebaki

et al. 2016

Materials Science in Semiconductor Processing

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Section: Resultsmentioning

confidence: 95%

Section: Resultsmentioning

confidence: 99%

Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

Bentrcia

Djeffal

Chebaki

et al. 2016

Materials Science in Semiconductor Processing

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“…However, the transconductance and drain current of CGT FET primarily vary with the change in input voltage reflecting the non‐linear behavior. To study the non‐linearity behavior of the present CGTS device, the drain current in Equation can be considered as a time varying non‐linear function

I_{d} = I_{0} + g_{m 1} V_{gs} + g_{m 2} {V_{italicgs}}^{2} + g_{m 3} {V_{italicgs}}^{3} + \dots + \dots

where I 0 represents the dc current and V gs is the applied input gate to source voltage.…”

Section: Resultsmentioning

confidence: 99%

Impact of source pocket doping on RF and linearity performance of a cylindrical gate tunnel FET

Dash

Lenka

Jena

et al. 2017

Int J Numerical Modelling

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The paper presents a cylindrical gate tunnel (CGT) field effect transistors (FETs) with a highly doped pocket layer introduced in the source region. The presence of pocket doped layer in the source provides higher lateral electric field and band‐to‐band tunneling (BTBT) generation rate in the vicinity of tunneling junction which in turn increases the drain current and transconductance significantly. Also, the linearity and radio frequency (RF) performance of the CGT FET with source pocket doping (CGTS) have been extensively investigated. The different linearity and RF figure of merits such as gmn, VIP2, VIP3, IIP3, ZCP, 1‐dB compression point, GBWP, TFP, unity gain cut‐off frequency, and maximum oscillation frequency of the present device are extracted and compared with the results of conventional CGT. The results exhibit superior linearity and RF performance along with improved current carrying capability of the proposed device. Thus, the device can be one of the possible contenders to replace bulk MOSFET in high‐frequency microwave applications. The accuracy of both the devices is validated by TCAD Sentaurus simulator.

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“…The most important design parameter for better sub-threshold swing and lower drain induced barrier of DG MOSFETs is the ratio of the fin width to the gate length. It has been widely known that the fin width in DG MOSFETs should be less than 0.7 times of the gate length for proper suppression of short channel effects [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology

Ghosh

Bhulania

Kumar

2015

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)

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This paper presents the analytical modeling of Gate All Around MOSFET using the Poisson's equation. Gate All Around MOSFET is experimentally demonstrated using a silicon channel. The analyzed model shows the close agreement with the simulation results. Atlas-3D tool has been used for the numerical simulations. A good performance has been achieved by scaling of the channel length to 50 nm with top-down approach. Our designed MOSFET follows the traditional MOSFET behavior inspite of enormous scaling and negligible hot carrier effects. The proposed model gives the simplest analysis in comparison to quantum models. Leakage current is negligible due to the use of bulk substrate which easily suppressed the adverse effect of parasitic capacitance. Simulated graph strongly follows the parabolic equation along the channel region for surface potential.

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Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis

Cited by 50 publications

References 30 publications

Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

Impact of source pocket doping on RF and linearity performance of a cylindrical gate tunnel FET

An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology

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