Effect of low and high temperature anneal on process-induced damage of gate oxide

King, J.C.; Hu, Chenming

doi:10.1109/55.334672

Cited by 65 publications

(19 citation statements)

References 5 publications

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“…One may safely conclude that a 400 C 30-min forming gas anneal has little impact on the concentration of the traps that cause oxide breakdown. This is in complete agreement with data obtained in thicker (85 ) oxide by King et al [26] and Furukawa et al [27].…”

Section: Methodssupporting

confidence: 90%

Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?

Pantisano

Cheung

2001

IEEE Trans. Device Mater. Relib.

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Many research groups have used stress-induced leakage current (SILC) as a mean to measure the oxide traps (defects) buildup in the oxide film during electrical stress. It is commonly believed that these very same traps will lead to oxide breakdown when their density reaches a critical value. We studied the annealing kinetic of SILC as well as the oxide breakdown distribution and found that they are quite different. Our result casts serious doubt on the validity of the popular assumption.

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Section: Methodssupporting

confidence: 90%

Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?

Pantisano

Cheung

2001

IEEE Trans. Device Mater. Relib.

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“…The trapped negative charge in the ONO layer affects the V th of the cell. As the measured subthreshold slope values do not show mismatching behavior, we assume that the plasma-induced interface states in both cell and transistor are annealed by the thermal budget [8]. We propose that the larger plasma-induced bulk trapped charge in the tunnel oxide of the transistor is the primary cause of the statistically lower mobility in comparison with the cell.…”

Section: Resultsmentioning

confidence: 99%

Intrinsic Mismatch Between Floating-Gate Nonvolatile Memory Cell and Equivalent Transistor

Duane

Rafhay²,

Beug³

et al. 2007

IEEE Electron Device Lett.

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The matching performance of nonvolatile memory cells and their equivalent transistors is investigated using a novel matching-performance factor. Extensive measurements on three technologies show that matching pairs can be found, but there is an inherent mobility mismatch between the equivalent transistor and the memory cell. It is suggested that the cause of this mismatch is due to the necessary layout differences between the cell and the equivalent transistor that can cause different levels of plasmainduced damage in the structures.

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“…2 shows VT degradation in NMOS devices under positive diagnostic F-N stress. Clear dependence on the amount of latent charging damage can be observed during the whole stress time.…”

Section: Stress-generated Electron Trapsmentioning

confidence: 99%

Threshold voltage degradation in plasma damaged cmos transistors - role of electron and hole traps related to charging damage

Brozek¹,

Chan²,

Viswanathan³

Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis

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The paper presents results of study of threshold voltage (VT) degradation in CMOS transistors damaged by high-field charging. Fowler-Nordheim stress induced VT degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. "Direct" and "reverse" antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously.Copyright 0 1996

show abstract

Effect of low and high temperature anneal on process-induced damage of gate oxide

Cited by 65 publications

References 5 publications

Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?

Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?

Intrinsic Mismatch Between Floating-Gate Nonvolatile Memory Cell and Equivalent Transistor

Threshold voltage degradation in plasma damaged cmos transistors - role of electron and hole traps related to charging damage

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