Effect of rapid thermal annealing on threading dislocation density in III-V epilayers monolithically grown on silicon

Li, W.; Chen, Siming; Tang, Mingchu; Wu, Jiang; Hogg, R. A.; Seeds, A.J.; Liu, Huiyun; Ross, I. M.

doi:10.1063/1.5011161

Cited by 15 publications

(12 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The effects of TCA and different DFLs on the TDD within GaAs buffer layers grown on Si were first studied by ECCI. Figure 2(a) shows the surface of the original unoptimised 1.4 µm GaAs buffer grown on Si substrate with a TDD of ∼10 9 cm −2 , which is reduced to the level of 1.21 × 10 8 cm −2 , as shown in figure 2(b) after being subjected to a common practice of TCA process before growing the DFLs [23,24]. The representative surface ECCI images of InAlGaAs ASG, InGaAs/GaAs SLSs, and InGaAs ASG are shown in figures 2(c)-(e), respectively, where all the TDs are marked by red hollow circles.…”

Section: Resultsmentioning

confidence: 99%

The growth of low-threading-dislocation-density GaAs buffer layers on Si substrates

Dang

Deng

Huo

et al. 2023

J. Phys. D: Appl. Phys.

Self Cite

View full text Add to dashboard Cite

Monolithic integration of III-V optoelectronic devices on Si platform is gaining momentum, since it enables advantages of low cost, less complexity and high yield for mass production. With the aim of achieving advances in monolthic integration, the challenges associated with lattice mismatch between III-V layers and Si substrates must be overcome, as a low density of threading dislocations is a prerequisite for the robustness of the integrated devices. In this paper, we have investigated and compare different tyeps of dislocation filter layers (DFLs) from InGaAs asymmetric step-graded buffer layer (ASG), InGaAs/GaAs strained-layer superlattices, and quaternary alloy InAlGaAs ASG, on the functionlity of reducing threading dislocation density (TDD) for GaAs buffer layers on Si. Compared to other DFLs, the sample with InAlGaAs ASG buffer layer shows the lowest average TDD value and roughness, while the deccrease of TDD in the sample with InAlGaAs ASG buffer layer can be understood in terms of the hardening agent role of aluminium in the InAlGaAs ASG. By further optimising the InAlGaAs ASG through thermal cyclic annealing, we successfully demonstrate a low surface TDD of 6.3±0.1×106 /cm2 for a 2 µm GaAs/InAlGaAs ASG buffer layer grown on Si. These results could provide a thin buffer design for monolthic integration of various III-V devices on Si substrates.

show abstract

Section: Resultsmentioning

confidence: 99%

The growth of low-threading-dislocation-density GaAs buffer layers on Si substrates

Dang

Deng

Huo

et al. 2023

J. Phys. D: Appl. Phys.

Self Cite

View full text Add to dashboard Cite

show abstract

“…It should be noted that a surface TDD lower than 2 × 10 6 cm -2 was obtained after a step-graded filter layer was grown on the post-TCA GaAs-on-Si. In a similar mechanism of TCA, post-growth annealing (PGA), carried out after completing the growth, has also been widely employed to reduce the TDD of GaAs [207][208][209]. For the InP/Si, TCA or PGA has also been applied to improve the crystal quality [168,169,210,211].…”

Section: Thermal Annealingmentioning

confidence: 99%

Heteroepitaxial Growth of III-V Semiconductors on Silicon

et al. 2020

View full text Add to dashboard Cite

Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.

show abstract

“…This would greatly reduce the internal quantum efficiency of the gain medium [48] . By optimizing the growth conditions and various measures to lower the dislocation density, such as double steps obtained by substrate annealing at high temperature [49,50] , offcut substrate [24] , V-groove [25] , U-shaped patterned Si (001) substrate [47,51] , GaP buffer layer [45,52] , Ge buffer layer [53] , lowtemperature seed layer [24,47,54] , dislocation filter layer (DFL) [48,55] and thermal cycle annealing [56] , the negative effects brought from the mismatches between the GaAs and Si have been significantly reduced. The TDs density is decreased by several orders of magnitude to 10 5 cm -2 [24] , as shown in Fig.…”

Section: Quantum Dot Laser On Si Substratementioning

confidence: 99%

Silicon photonic transceivers for application in data centers

Wang

Chai

et al. 2020

J. Semicond.

View full text Add to dashboard Cite

Global data traffic is growing rapidly, and the demand for optoelectronic transceivers applied in data centers (DCs) is also increasing correspondingly. In this review, we first briefly introduce the development of optoelectronics transceivers in DCs, as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process. We also summarize the research on the main components in silicon photonic transceivers. In particular, quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts. Some of the solutions for high-speed optical interconnection in DCs are then discussed. Among them, wavelength division multiplexing and four-level pulse-amplitude modulation have been widely studied and applied. At present, the application of coherent optical communication technology has moved from the backbone network, to the metro network, and then to DCs.

show abstract

Effect of rapid thermal annealing on threading dislocation density in III-V epilayers monolithically grown on silicon

Cited by 15 publications

References 28 publications

The growth of low-threading-dislocation-density GaAs buffer layers on Si substrates

The growth of low-threading-dislocation-density GaAs buffer layers on Si substrates

Heteroepitaxial Growth of III-V Semiconductors on Silicon

Silicon photonic transceivers for application in data centers

Contact Info

Product

Resources

About