Effect of source and drain asymmetry on hot carrier degradation in vertical nanowire MOSFETs

Lee, Jae Hoon; Han, Jin−Woo; Yu, Chong Gun; Park, Jong-Tae

doi:10.1016/j.microrel.2015.06.062

Microelectronics Reliability

2015

DOI: 10.1016/j.microrel.2015.06.062

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Effect of source and drain asymmetry on hot carrier degradation in vertical nanowire MOSFETs

Jae Hoon Lee

Jin−Woo Han

Chong Gun Yu

et al.

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Cited by 4 publications

(1 citation statement)

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“…Second, in terms of packing density, the horizontal nanowire FET is preferred because its foot print in layout is not increased as long as the multiple nanowires are vertically stacked. Third, the inherent asymmetric S/D resistance arisen from the vertical configuration of the pillar is problematic as reported elsewhere. , Thus, the development of an optimal structure that satisfies high I ON and good scalability simultaneously is required. The best strategy is to combine the GAA structure to suppress SCEs for ultimate scalability and a vertically integrated NW structure to maximize the I ON current for high performance.…”

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confidence: 99%

Vertically Integrated Multiple Nanowire Field Effect Transistor

et al. 2015

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A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

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Vertically Integrated Multiple Nanowire Field Effect Transistor

et al. 2015

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Stacked Lateral Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors and Their Three-Dimensional Integrated Circuits

Liu

et al. 2022

Silicon

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According to the International Roadmap for Devices and Systems, gate-all-around (GAA, also known as a surrounding gate) metal–oxide–semiconductor field-effect transistor (MOSFET) will be the main device in integrated circuits (ICs). Lateral GAA (LGAA) MOSFETs have been applied in CMOS logic circuits from a 3-nm technology node. However, further shrinkage of the contacted gate pitch is difficult owing to the physics and processing limitations. Three-dimensional (3D) stacking of chips or wafers is therefore widely studied for high integration. However, the device distance between stacked chips or wafers is rarely less than 10 µm, which is too long considering the electrical resistance and transfer delay, especially for logic circuits. Complementary field-effect transistors are currently a widely used 3D logic device; however, a compatible process is required for the heterostructures. The authors previously developed a fabrication process for symmetric-source/drain vertical GAA (referred to as ultimate VGAA, UVGAA) MOSFET for the first time; a novel architectural 3D IC with stacking UVGAA-based devices (CMOS and/or SRAM) in the vertical direction was also developed. In this perspective, a fabrication process for stacked LGAA (SLGAA) MOSFETs in the vertical direction is proposed for the first time and a high integration 3D logic IC based on SLGAA MOSFETs is also developed. These novel 3D architectures lay the foundations for next-generation ICs.

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Ultimate vertical gate-all-around metal–oxide–semiconductor field-effect transistor and its three-dimensional integrated circuits

Yamabe

Endoh

2021

Materials Science in Semiconductor Processing

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Effect of source and drain asymmetry on hot carrier degradation in vertical nanowire MOSFETs

Cited by 4 publications

References 8 publications

Vertically Integrated Multiple Nanowire Field Effect Transistor

Vertically Integrated Multiple Nanowire Field Effect Transistor

Stacked Lateral Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors and Their Three-Dimensional Integrated Circuits

Ultimate vertical gate-all-around metal–oxide–semiconductor field-effect transistor and its three-dimensional integrated circuits

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