Effect of source/drain-extension dopant species on device performance of embedded SiGe strained p-metal oxide semiconductor field effect transistors using millisecond annealing

Illgen, R.; Flachowsky, S.; Herrmann, T.; Klix, W.; Stenzel, R.; Feudel, Thomas; Höntschel, J.; Horstmann, Μ.

doi:10.1116/1.3244578

Cited by 4 publications

(3 citation statements)

References 4 publications

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“…Illgen et al have reported that S/D extension implantation using BF 2 þ ions at an energy of 2.3 keV and a dose of 1:2 Â 10 15 /cm 2 causes amorphization of the top layer of the SiGe regions. 12) We also observed in our results an amorphous SiGe peak at $475 cm À113) (out of displayed range) for the implanted sample. On a separate note, we see that the characterization method used here enables useful information to be acquired simultaneously for the SiGe regions as well as for the Si channels.…”

supporting

confidence: 81%

Impact of Implantation and Annealing on Channel Strain of Transistors with Embedded Silicon–Germanium Source and Drain

Wong¹,

Liu

Kasim

et al. 2011

Jpn. J. Appl. Phys.

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We investigate the effect of implantation and annealing on 45 nm node transistors with embedded silicon–germanium source and drain, using UV Raman spectroscopy. Direct measurements of the channel strain indicate that the strain relaxed after implantation is recovered partially after annealing. Recovery of channel strain depends on annealing conditions. Our results show that a low-temperature, long-duration anneal results in a greater channel strain compared to a high-temperature, short-duration anneal. When a high-temperature anneal is needed for fabricating transistors, a two-step anneal involving a low-temperature furnace anneal prior to a high-temperature rapid thermal anneal can be beneficial for recovering channel strain.

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supporting

confidence: 81%

Impact of Implantation and Annealing on Channel Strain of Transistors with Embedded Silicon–Germanium Source and Drain

Wong¹,

Liu

Kasim

et al. 2011

Jpn. J. Appl. Phys.

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“…However, likely due to the emphasis on the engineering aspects of their work, no information was provided on the kind of physical models or framework used for their TCAD strain simulations. Nevertheless, these works paved the way for using TCAD tools (notably from Synopsys) for simulating strains and the resulting electrical behavior in strain-engineered MOSFETs [35][36][37][38][39][40][41][42][43] after simulating the strained structures from the TCAD process tool, one will then input the results into the TCAD device tool to simulate the electrical behavior of the devices. (Note: TCAD process simulation tools model the fabrication steps of semiconductor devices.…”

Section: Simulationsmentioning

confidence: 99%

“…Significant defect formation in SiGe is also implied by the decrease in relative intensity and the broadening of this peak. Illgen et al[36] have reported that S/D extension implantation using BF 2 + ions at an energy of 2.3 keV and dose of 1.210 15 cm -2 causes amorphization of the top layer of the embedded SiGe. On a separate note, we see how the method of characterization employed here enables useful information to be acquired simultaneously for the embedded SiGe regions as well as for the Si channels.…”

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confidence: 99%

UV Raman studies of channel stress in transistors with embedded SiGe source and drain

Wong¹

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engineering technique, SiGe, which is epitaxially grown in the source and drain regions, acts as a stressor to induce a compressive strain in the channel. By varying the Ge concentration, it is possible to increase or decrease the amount of strain. Ever since the first report of this strain technology appeared in the International Electron Devices Meeting in 2002 [3], it has rapidly gained popularity and has become the main method for inducing compressive strain in p-type MOSFETs in production nowadays. 1.2 Overview of this thesis We begin with a literature review in Chapter 2. This chapter is divided into two main sections. The first section briefly reviews the field of MOSFETs with strained silicon channels. This section includes a description of the main physical mechanisms behind the improvement in carrier mobility when silicon is appropriately strained. It also provides information on the methods commonly used to strain the transistor channels. This section then moves on to describe the available methods that are used to quantify channel strain. Both simulation and experimental methods will be covered. A discussion of the strengths and limitations of current experimental methods, as well as the lack in studies in certain areas is then given. The second section of this chapter reviews the theory underlying the Raman scattering of semiconductors. Also included is the theory addressing the change in the Raman characteristics of silicon when a uniaxial stress is applied to it. Next, the materials, instrumentation, and methods used for the work in this thesis are given in Chapter 3. The process flow for the devices used is briefly described under the Materials section. For the Instrumentation and Methods section, details of the hardware and operation of our Raman spectroscopy system are provided. Relevant concepts such as spatial and spectral resolution are explained. Also described in this section are the finite-ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library CHAPTER 1: INTRODUCTION 3 difference time-domain (FDTD) method and the software program used for such work in the thesis. Chapters 4 to 6 cover the main projects undertaken for this thesis. Chapter 4 lays the foundation that Chapters 5 and 6 build upon. The sample preparation method, approach for channel stress measurements, and data analysis and interpretation are given in Chapter 4. Chapter 5 extends the research to study the effect of implantation and annealing on the channel stress. Chapter 6 includes FDTD simulations to provide insight into the distribution of the Raman excitation light in the structures studied in Chapters 4 and 5. Implications of using Raman excitation light of different polarizations are discussed. Chapter 7 then follows. This brief chapter contains some results of near-field Raman mapping for high spatial resolution work. Finally, Chapter 8 highlights the main conclusions of the work in this thesis and provides suggestions for further work. Note: Unless otherwise ...

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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate

Lee

Majhi

Ferrer

et al. 2011

IEEE Trans. Electron Devices

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Effect of source/drain-extension dopant species on device performance of embedded SiGe strained p-metal oxide semiconductor field effect transistors using millisecond annealing

Cited by 4 publications

References 4 publications

Impact of Implantation and Annealing on Channel Strain of Transistors with Embedded Silicon–Germanium Source and Drain

Impact of Implantation and Annealing on Channel Strain of Transistors with Embedded Silicon–Germanium Source and Drain

UV Raman studies of channel stress in transistors with embedded SiGe source and drain

Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate

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