Effect of substrate negative bias on GIDL current in LDD nMOSFET's

GIDL and gated diode tests are useful to probe the integrity of surface channel. In this work, the latter seems better to the former in detecting the trapping/detraaping on the channel surface. As V G~ -0.62V, the peak effect of drain current was observed for gate diode test, but not apparent for GIDL test for all of tested devices even though the gate bias was swept back and forth at the accumulation mode of nMOSFETs. The decoupled plasma nitridation treatment for HK dielectric with both annealing temperatures shows the trap amount with the higher annealing is less than that with the lower one at the middle vertical field operation, but the whole drain leakage with the lower annealing is better than that with the higher one as V G =-Vcc due to the high possibility to form the micro-or nano-crystallization causing the huge PooleFrenkel tunneling.

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Effect of substrate negative bias on GIDL current in LDD nMOSFET's

Cited by 2 publications

References 8 publications

GIDL Analysis of 1T1C Structure for Sub-20nm DRAM Cell

GIDL Analysis of 1T1C Structure for Sub-20nm DRAM Cell

GIDL and gated-diode metrologies for 28nm HK/MG nMOSFETs in nitridation annealing temperatures

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