2010
DOI: 10.1080/15980316.2010.9652111
|View full text |Cite
|
Sign up to set email alerts
|

Effective annealing and crystallization of si film for advanced TFT system

Abstract: The effect of the crystallization and activated annealing of Si films using an excimer laser and the new CW blue laser are described and compared with furnace annealing for application in advanced TFTs and for future applications. Pulsed excimer laser annealing (ELA) is currently being used extensively as a low-temperature poly-silicon (LTPS) process on glass substrates as its efficiency is high in the ultraviolet (UV) region for thin Si films with thickness of 40-60 nm. ELA enables extremely low resistivity r… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2015
2015
2021
2021

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 12 publications
0
2
0
Order By: Relevance
“…These values are a little higher than the resistivity of the poly-Si film formed by other low-temperature poly-Si processes. For instance, according to T. Noguchi, 34) the lowest resistivity of P-doped Si film formed by excimer laser annealing with a pulse energy density of 350 mJ cm −2 is 4.2 × 10 −4 Ωcm. In principle, these values are suitable for transistor fabrication.…”
Section: Hall Effect Measurement's Resultsmentioning
confidence: 99%
“…These values are a little higher than the resistivity of the poly-Si film formed by other low-temperature poly-Si processes. For instance, according to T. Noguchi, 34) the lowest resistivity of P-doped Si film formed by excimer laser annealing with a pulse energy density of 350 mJ cm −2 is 4.2 × 10 −4 Ωcm. In principle, these values are suitable for transistor fabrication.…”
Section: Hall Effect Measurement's Resultsmentioning
confidence: 99%
“…The poly-Si channel layer was transformed from an a-Si layer using a laser annealing process. Therefore, multiple grain boundaries (GBs) are expected because of the grain impediment during the grain growth [40]. Multiple GBs in a poly-Si layer have been verified and are normally considered in the studies of poly-Si TFTs [37,38,41].…”
Section: Device Fabrication and Simulation Methodologymentioning
confidence: 99%