Effective compiler support for predicated execution using the hyperblock

Mahlke, Scott; Lin, David C.; Chen, William Y.; Hank, Richard E.; Bringmann, Roger A.

doi:10.1145/144965.144998

Cited by 270 publications

(210 citation statements)

References 11 publications

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“…Specifically, all control dependencies within the code region targeted for elastic-block formation are converted into data dependencies, similarly to what is done, e.g., in hyperblock [12], conditional branches are replaced with comparison instructions which set the final predicate of all instructions that are control dependent on such branches. Even if generated using well known techniques, the final predicate is a very unique operand type in our target dataflow ISA, in that an instruction may actually execute even if the value of its final predicate is still unknown.…”

Section: Power Aware Ilp Extraction With Elastic-blocksmentioning

confidence: 99%

“…Note that, the semantics of our final predicate is, thus, somewhat different form that of the standard predication model adopted, for example in [13], due to performance reasons, instructions always execute, and their predicates are only used to decide if their results should be committed or not. Reflecting that fact, traditional hyperblock selection approaches, such as [12], do not favour the inclusion of large basic-blocks in a hyperblock, since such blocks utilize many machine resources and may actually end up negatively impacting performance, as opposed to enhancing it. As will be seen below, the elastic-block's increased flexibility enables such aggressive performance-enhancing ILP extraction techniques to be enhanced with energy awareness and efficiency considerations.…”

Section: Power Aware Ilp Extraction With Elastic-blocksmentioning

confidence: 99%

“…Compared to 'hyperblock' [12], 'elastic-block' is capable of achieving more power-performance trade-off points. During hyperblock formation a basicblock is either fully included or fully excluded.…”

Section: Power-performance Trade-off Using Compiler Analysismentioning

confidence: 99%

“…Mahlke et al proposed a compiler structure, hyperblock, that groups together most frequently executed basic-blocks from different control paths, allowing effective scheduling for these basic-blocks [12]. In case of an hard-to-predict branch (say 60/40), basic-blocks from 'both' control-flow paths are included in the hyperblock , and all instructions in these basic-blocks are executed all the time.…”

Section: Predication For Superscalar Architecturesmentioning

confidence: 99%

See 3 more Smart Citations

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Farooq

John

Jacome

2009

High Performance Embedded Architectures and Compilers

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Abstract. Traditional predicated execution uses two techniques: top predication -in which only the head of the dependence chain is predicated, and bottom predication -in which only the tail of the dependence chain is predicated. Top predication prevents speculative execution, thus delivering minimum performance at minimum energy cost, while bottom predication allows full speculation of the dependence chain, resulting in maximum performance at maximum energy cost. In this paper, we propose a novel power-aware ILP extraction technique, denoted the 'elasticblock', that combines these two extremes, exposing superior energy vs. performance trade-offs. Each instruction in the elastic-block is explicitly guarded by two predicates: the speculative, and the final. Instruction's final predicate is generated using traditional if-conversion technique, while the speculative predicate has its default value statically assigned by the compiler, enabling it to make power-performance trade-offs in the code. Several energy saving code optimizations are proposed for the elasticblock structure.

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Section: Power Aware Ilp Extraction With Elastic-blocksmentioning

confidence: 99%

Section: Power Aware Ilp Extraction With Elastic-blocksmentioning

confidence: 99%

Section: Power-performance Trade-off Using Compiler Analysismentioning

confidence: 99%

Section: Predication For Superscalar Architecturesmentioning

confidence: 99%

See 2 more Smart Citations

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Farooq

John

Jacome

2009

High Performance Embedded Architectures and Compilers

View full text Add to dashboard Cite

show abstract

“…We choose hyperblock [16] as the basic structure in our CRCP algorithm. A hyperblock is a set of predicated basic blocks in which control may only enter from the top, but may exit from one or more locations.…”

Section: Basic Crcp Algorithmmentioning

confidence: 99%

Power Modeling and Reduction of VLIW Processors

Liao

2003

Compilers and Operating Systems for Low Power

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In this paper, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows the designer to evaluate both VLIW compiler and microarchitecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CRCP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CRCP respectively.

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Building a retargetable local instruction scheduler

Allan

Beaty

et al. 1998

Softw: Pract. Exper.

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SUMMARYWhile high-performance architectures have included some Instruction-Level Parallelism (ILP) for at least 25 years, recent computer designs have exploited ILP to a significant degree. Although a local scheduler is not sufficient for generation of excellent ILP code, it is necessary as many global scheduling and software pipelining techniques rely on a local scheduler. Global scheduling techniques are well-documented, yet practical discussions of local schedulers are notable in their absence. This paper strives to remedy that disparity by describing a list scheduling framework and several important practical details that, taken together, allow implementation of an efficient local instruction scheduler that is easily retargetable for ILP architectures.The foundation of our machine-independent instruction scheduler is a timing model that allows easy retargetability to a wide range of architectures. In addition to describing how a general listscheduler can be implemented within the framework of our timing model, experimental results indicate that lookahead scheduling can profoundly improve a scheduler's ability to produce a legal schedule. Further experimental data shows that deciding to schedule a data dependence DAG (DDD) in forward or reverse order depends significantly upon that target architecture, suggesting the possibility of scheduling in each direction and using the best of the two schedules.In contrast, experiments demonstrate little difference in code quality for schedules generated by either instruction-driven or operation-driven schedulers. Thus, the inherent flexibility of operationdriven methods suggests including that approach in a retargetable instruction scheduler.List scheduling is, of course, a heuristic scheduling method. A variety of scheduling heuristics are presented. In addition, the paper describes a method, using a genetic algorithm search, to 'fine-tune' the weights of twenty-four individual heuristics to form a DDD-node heuristic tuned to a specific architecture.

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Effective compiler support for predicated execution using the hyperblock

Cited by 270 publications

References 11 publications

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Power Modeling and Reduction of VLIW Processors

Building a retargetable local instruction scheduler

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