Power Modeling and Reduction of VLIW Processors

Liao, Weiping; He, Lei

doi:10.1007/978-1-4419-9292-5_9

Cited by 7 publications

(4 citation statements)

References 19 publications

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“…The energy efficiency of the VLIW architecture is determined by the underlying hardware and compiler technologies. In order to support efficient exploration of the energy tradeoffs of different architectural configurations and compiler optimizations, different architectural level energy estimation tools have been proposed for VLIW architectures in Kim et al [2001], Sami et al [2000], and Liao and He [2001]. An instruction-level energy estimation methodology has been proposed for exploring different architectural topologies for VLIW architectures Sami et al [2000].…”

Section: Related and Future Workmentioning

confidence: 99%

Reducing dynamic and leakage energy in VLIW architectures

Zhang

Tsai

Duarte

et al. 2006

ACM Trans. Embed. Comput. Syst.

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The mobile computing device market has been growing rapidly. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in the future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present three compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. Integer ALU (IALU) components operating with multiple supply voltages are designed to provide different lowenergy versions that possess different operational latencies. The goal of the first technique explored is to maximize the number of operations mapped to IALU components with the lowest energy consumption without extending the schedule length. We also consider a variant of this technique that saves more energy at the cost of some performance loss. The second technique uses two leakagecontrol mechanisms to reduce leakage energy consumption when no operations are scheduled in the component. Our evaluation of these two approaches, using fifteen benchmarks, shows that based on the number and duration of slacks, the availability of low-energy functional units and the relative magnitude of leakage and dynamic energy, either leakage or dynamic energy consumption, will provide more energy gains. Finally, we provide a unified energy-optimization strategy that integrates both dynamic and leakage energy-reduction schemes. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit-level simulation. Our results show that the unified scheme generates better results than using either of dynamic and leakage energy-reduction techniques independently.

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Section: Related and Future Workmentioning

confidence: 99%

Reducing dynamic and leakage energy in VLIW architectures

Zhang

Tsai

Duarte

et al. 2006

ACM Trans. Embed. Comput. Syst.

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“…We utilize four different tools in this evaluation: We use the Simplescalar out-of-order [16], which is used for simulating the dynamic scheduled architecture and analyzing performance, and the Trimaran [17] tool for static scheduled architecture simulation and performance evaluation. We also use the tool Wattch [8] to estimate the power dissipation on superscalar architecture for each application and we use the tool PowerImpact [10] to estimate power consumption of VLIW architecture. In the static scheduling simulation using Trimaran, we use three region formations for front-end compiler optimization, which is independent of the target processor, in order to see the effectiveness of aggressive compiler optimization techniques.…”

Section: Experimental Frameworkmentioning

confidence: 99%

Exploiting Statically Identified ILP for Network Processor Applications

Lee¹

2010

IJCEE

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Abstract-Along with sharply increasing bandwidth requirements, modern network applications and new protocols demand highly intelligent and sophisticated processing over the network. Since these workloads require processing capability beyond state-of-the-art microprocessors, parallel architectures are required in order to handle the packet data without slowing down line speed. Network processors with various parallel architectures are appearing in the market, however, a thorough investigation of the implications of static versus dynamic scheduling of this class of emerging workloads has not been done. In this paper, we characterize the performance and power dissipation of statically identified ILP architectures, and we also compare them to dynamically scheduled architectures for network processing. In dynamically scheduled architectures, the power consumption of the instruction window greatly increases with increasing issue widths. On the other hand, statically scheduled architectures show better performance, as well as tremendous advantages in power, since they do not have instruction window wakeup/select, reorder buffer, and other scheduling related hardware modules. With the large parallelism and the loop nature of network applications, our experimental analysis supports static scheduling as an appropriate strategy for network processor applications.

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“…A micro-architectural power-model based on the Cai-Lim technique 14 was presented in Ref. 33. Their tool, PowerImpact, was integrated in the Impact VLIW simulation environment.…”

Section: Vliw Microprocessorsmentioning

confidence: 99%

Matador: An Exploration Environment for System-Design

Marchal

Jayapala²,

Xavier‐de‐Souza

et al. 2002

J CIRCUIT SYST COMP

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We present a modular platform simulation environment to estimate the energy consumption and performance of distributed systems in a Systems-on-Chip context. We use the simulation environment to support the development of our high-level design methodologies. More in particular, we steer and verify the development of a task-level data transfer and storage methodology, the development of a task-level scheduling methodology and the development of an instruction memory management methodology. All of these methodologies are focussed on reducing the overall energy consumption of the complex dynamic system on a heterogeneous platform architecture. Compared to research in the academic and industrial context, our contribution is to integrate in a scalable way existing energy and performance simulators of the components of a heterogeneous multiprocessor SoC. Also a novel instruction memory hierarchy is included. The simulation environment consists of multiple processing nodes connected to a distributed memory hierarchy. To reduce the energy consumption of the system, both the processing nodes as well as the memory architecture can be varied: the processing voltage of each node can be tuned and the memory hierarchy can be fully customized. The integration of dynamic real-time applications on this platform is simplified by the availability of a multi-processor RTOS. The use of the simulator to develop our high-level design methodologies is illustrated on real-life multimedia applications.

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Power Modeling and Reduction of VLIW Processors

Cited by 7 publications

References 19 publications

Reducing dynamic and leakage energy in VLIW architectures

Reducing dynamic and leakage energy in VLIW architectures

Exploiting Statically Identified ILP for Network Processor Applications

Matador: An Exploration Environment for System-Design

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