Effective Data Transmission with UART on Kintex-7 FPGA

Kumar, Keshav; Kaur, Amanpreet; Ramkumar, K.

doi:10.1109/cicn49253.2020.9242604

Cited by 7 publications

(2 citation statements)

References 12 publications

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“…The three thermal possessions are related to FPGA which are termed such as Under operating conditions, it is expressed the temperature around the FPGA [21][22][23] (iii) Junction temperature (JT) ( °C). It is called as the operational temperature of the FPGA [5,24]. It is the aggregate total on chips power, effective TJA, and MAT [5] The thermal properties with all the voltage range of values for UART protocol for Artix-7 FPGA are represented in Figure 5.…”

Section: Thermal Properties For Different Voltage Valuesmentioning

confidence: 99%

Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

Haripriya

Kumar

Shrivastava³

et al. 2022

Wireless Communications and Mobile Computing

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In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.

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Section: Thermal Properties For Different Voltage Valuesmentioning

confidence: 99%

Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

Haripriya

Kumar

Shrivastava³

et al. 2022

Wireless Communications and Mobile Computing

Self Cite

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“…The time taken to move the information was reduced because of an increased baud rate. The authors in [3] implemented the data communication using clock periods above 3 ns on Kintex-7 FPGA. The design was analysed at various clock periods.…”

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confidence: 99%

Design and Implementation of Power-Efficient FSM based UART

Kamath

Mendez

Ramya

et al. 2022

J. Phys.: Conf. Ser.

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The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

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