Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

Chatterjee, B.; Sachdev, Manoj; Hsu, Steven; Krishnamurthy, Ram; Borkar, S.

doi:10.1145/871506.871538

Cited by 25 publications

(14 citation statements)

References 18 publications

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“…The reduction in the transistor OFF-state current due to supply scaling can be expressed as [12]: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Section: Supply Scaling and Transistor Currentsmentioning

confidence: 99%

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

Chatterjee

Sachdev

Krishnamurthy

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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Section: Supply Scaling and Transistor Currentsmentioning

confidence: 99%

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

Chatterjee

Sachdev

Krishnamurthy

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…To reduce the leakage power, other circuit techniques can be used such as MTCMOS, DTCMOS, Reverse Body Bias and larger than Vdd Forward Body Bias [15,16,17,18]. Borkar et al [11] have evaluated some of these techniques and have shown that the stack effect is the most effective means to reduce leakage power, but because it lowers the active current in the normal mode operation, it is also the slowest. They have also shown that lowering voltage is inferior in terms of both leakage savings as well as in speed (low voltage underrates Ion significantly).…”

Section: Related Workmentioning

confidence: 99%

“…However, the usage of RBB requires the generation and routing of extra power supply to the body and well terminals of n-and p-MOS transistors. In addition, it requires the usage of a triple-well bulk CMOS process [11] increasing the overall implementation cost. MTCMOS is in effect a dynamic implementation of the RBB scheme, which makes it more costly in terms of fabrication.…”

Section: Related Workmentioning

confidence: 99%

A simple mechanism to adapt leakage-control policies to temperature

Xekalakis

Κεραμίδας

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so far that can be broadly categorized into state-preserving (e.g., Drowsy Caches) and non-state preserving (e.g., Cache Decay). Decay saves more leakage but also incurs dynamic power overhead in the form of induced misses. Previous work has shown that depending on the leakage vs. dynamic power trade-off, one or the other technique can be better. Several factors such as cache architecture, technology parameters and temperature, affect this trade-off. Our work proposes the first mechanism -to the best of our knowledge-that takes into account temperature in adjusting the leakage control policy at run time. At very low temperatures, leakage is relatively weak so the need to tightly control it is not as important as the need to minimize extra dynamic power (e.g., decay-induced misses) or performance loss. We use a hybrid decay+drowsy policy where the main benefit comes from decaying cache lines while the drowsy mode is used to save leakage in long decay intervals. To adapt the decay mode to temperature, we propose a simple triggering mechanism that is based on the principles of decaying 4T thermal sensors and, as such, tied to temperature. The hotter the cache is, the faster cache lines are decayed since it is beneficial to do so with very high leakage currents.Conversely, when the cache temperature is low, our mechanism defers putting cache lines in decay mode to avoid dynamic power overhead but still saves a significant amount of leakage using the drowsy mode. Our study shows that across a wide range of temperatures, the simple adaptability of our proposal yields consistently better results than either the decay mode, or drowsy mode alone, improving over the best by as much as 33%.

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“…This percentage is expected to increase with technology scaling. Simulation results in [7] predict that the transistor off-state current per micron of transistor width increases by a factor of 3-5 per generation. As will be shown in Section 4, for a given package, the die temperature can be modeled as a linear function of the total power dissipation of the circuit.…”

Section: Introductionmentioning

confidence: 99%