Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs

Benware, B.; Madge, R.; Lu, Cheng-Tse; Daasch, R.

doi:10.1109/vtest.2003.1197631

Cited by 34 publications

(9 citation statements)

References 16 publications

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“…Effective screening of delay defects often requires a combination of parametric and nonparametric testing methods [12]. Past studies have demonstrated that the problem of drawing a reliable boundary between the good and the defective chips in delay testing is inherently statistical [13].…”

Section: Background and Related Workmentioning

confidence: 99%

Issues on Test Optimization with Known Good Dies and Known Defective Dies ¿ A Statistical Perspective

Lee

Wang

Abadir³

2006

2006 IEEE International Test Conference

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As the timing behavior of the good and defective chips become statistical, the traditional notion that there exists a one-dimensional timing boundary to separate the good and defective behavior may no longer be true. This paper studies issues in test optimization for screening statistical delay defects. After the first silicon tapeout, test data learning based on silicon samples can be utilized to optimize the test set for mass production. This approach depends on the availability of known good and known defective samples. This paper focuses the discussion on silicon sample based test optimization. We relate this problem to binary classification andpattern selection to thefeature selection problem in statistical learning. Experimental results are presented to explain the methodologies and the new concepts.

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Section: Background and Related Workmentioning

confidence: 99%

Issues on Test Optimization with Known Good Dies and Known Defective Dies ¿ A Statistical Perspective

Lee

Wang

Abadir³

2006

2006 IEEE International Test Conference

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“…Traditionally, test methods have been evaluated empirically. Specifically, silicon experiments are conducted to reveal real defect characteristics and for assessing the capability of various test and DFT methods to detect chip failures [4,5,14,16,17,[20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36]. Unique fallouts (i.e., chip-failure detections) are considered to be good indicators of relative effectiveness.…”

Section: Introductionmentioning

confidence: 99%

Test effectiveness evaluation through analysis of readily-available tester data

Lin

Blanton

2009

2009 International Test Conference

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Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. To reduce the cost of evaluating new test metrics, fault models, DFT techniques, etc., this work proposes a new approach that exploits the readily-available test-measurement data in chip-failure log files. The new approach does not require the generation and application of new patterns but uses analysis results from existing tests. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) PAN-detect (physically-aware N-detect), (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).

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“…While low-voltage testing methods (including variants called VLV testing [4] and MinVdd testing [5]) have been extensively studied, less literature is available on testing with lowered temperature. Nevertheless, the effectiveness of lowtemperature test has been demonstrated for three (real) defect classes at Intel [6] and was investigated on real silicon in [7].…”

Section: Introductionmentioning

confidence: 99%

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing

Kundu

Engelke

Polian

et al. 2005

14th Asian Test Symposium (ATS'05)

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Resistive defects are gaining importance in very-deepsubmicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is the first analytical study of resistive bridge defect coverage of CMOS ICs under low-temperature and mixed low-temperature, low-voltage conditions. We extend a resistive bridging fault model in order to account for temperature-induced changes in detection conditions. We account for changes in both the parameters of transistors involved in the bridge and the resistance of the short defect itself. Using a resistive bridging fault simulator, we determine fault coverage for low-temperature testing and compare it to the numbers obtained at nominal conditions. We also quantify the coverage of flaws, i.e. defects that are redundant at nominal conditions but could deteriorate and become earlylife failures. Finally, we compare our results to the case of low-voltage testing and comment on combination of these two techniques.

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Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs

Cited by 34 publications

References 16 publications

Issues on Test Optimization with Known Good Dies and Known Defective Dies ¿ A Statistical Perspective

Issues on Test Optimization with Known Good Dies and Known Defective Dies ¿ A Statistical Perspective

Test effectiveness evaluation through analysis of readily-available tester data

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing

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