Effectiveness of low power dual-V/sub t/ designs in nano-scale technologies under process parameter variations

A Review on Random Dopant Fluctuation Impact on Within-Die Variation

“…The relationship between RDF and the threshold voltage is shown in Fig .3. A very important observation is that, for a given technology RDF is increasing dramatically as threshold voltage increases and especially in smaller technologies (for 9nm, more than 50% increase in σRDF between =50 and 200mV) as in [1]. Thus, if σRDF needs to be reduced, the threshold voltage has to be reduced as well.…”

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

“…To the best of our knowledge, the last paper, [21], was the only paper to address the impact of process variation considering multi-Vt designs. In this paper, we address this issue from a different angle to show how multi-Vt design can be used to reduce the impact of variation and, at the same time, to reduce static power consumption.…”

“…This problem is referred to as threshold voltage variation due to random dopant fluctuation (RDF), and it is considered a major problem in current technologies and expected to be worse in future technologies [18,21,22]. Since in smaller technologies, the total number of dopants is expected to be lower; thus, the problem is likely to be worse [11,20].…”

“…The authors in [21] show the relationship between the standard deviation in threshold voltage due to RDF versus the threshold voltage value for sub 32 nm technologies [14,21]. Fig.…”

Exploring Very Low-Energy Logic: A Case Study

“…6 In transistors with channel lengths below 50 nm, band-to-band tunneling (BTBT) can dominate I off , negating the effect of using relatively higher threshold voltages. 7 A review of several low leakage techniques and how they affect the total energy of a CMOS gate is conducted in Section 2, then Section 3 presents pass transistor logic (PTL) as a good alternative to low leakage logic design. Section 4 introduces the sense amplifier-based pass transistor logic (SAPTL) topology as a low leakage circuit alternative that allows continued energy reduction through voltage scaling even in the presence of leakage and discusses the organization and synchronous timing operation of the SAPTL.…”