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This paper shows leakage as a limit to the effectiveness of voltage scaling as a means of reducing the energy per operation in a digital circuit. Methods of decreasing operational or dynamic leakage are then discussed. The design and simulation results of a sense amplifier-based pass transistor logic (SAPTL) circuit topology as a low leakage and low energy alternative is presented and then compared to standard static 90-nm CMOS implementations.

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With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental noise. On the other hand, as long as all errors can be detected and recovered, a considerable amount of energy can be saved.In this paper, a processor based on the ARM architecture was first implemented and verified, and then the RAZOR technique was integrated to add resiliency. The core with and without RAZOR are then simulated using an FFT program at different supply voltages and clock frequencies.The optimized core achieved a maximum energy reduction of 22% at constant clock frequency, while a 23% performance increase is observed at constant energy consumption.

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