Effects of Area Ratio on the Characteristics of Metal-Ferroelectric-Metal-Insulator-Semiconductor Field-Effect-Transistors (MFMIS FETs)

Abstract

The switching physics of ferroelectric, series capacitance theory and Pao and Sah’s double integral are used for describing the polarization-voltage (P-V) characteristic of ferroelectric layer, capacitance-voltage (C-V) characteristic of MFMIS capacitor, and drain current-gate voltage (ID-VGS) and drain current-drain voltage (ID-VDS) characteristics of MFMIS FET. The effects of the area ratio on the P-V, C-V, ID-VGS, and ID-VDS characteristics are discussed. The results indicate that with the increase of the area ratio, the P-V characteristic, memory windows of C-V and ID-VGS characteristics become saturated, while the drain current ON/OFF ratio and applied voltage for saturated memory window decrease.

High performance ferroelectric field-effect transistors for large memory-window, high-reliability, high-speed 3D vertical NAND flash memory

“…Additionally, the overall dispersion of the grain size increased with the median value, which resulted from the relative decrease in the bulk free energy of the monoclinic phase and its formation is accelerated as the grain size increased. 18 The increase in the paraelectric m-phase led to the deterioration of the ferroelectricity, as shown in Fig. 2(a).…”

“…As a future 3D nonvolatile memory device, we present a 3D ferroelectric NAND flash array and its optimal operation scheme that can alleviate the intrinsic problem of an increase in the lateral footprint of a planar structure-based MFMIS FeFET. 17,18 The proposed operation scheme of 3D ferroelectric NAND flash was proven to be suitable for multi-string operations free from program/erase disturbances, as verified by technology computer-aided design (TCAD) simulations with a carefully calibrated model. We believe that 3D ferroelectric NAND flash memory is a powerful candidate for next-generation nonvolatile memory devices owing to its superior performance.…”