Effects of copper plating thickness of Ni/Fe alloy leadframe on the thermal performance of Small Outline Transistor (SOT) packages

Abstract

Small Outline Transistor (SOT) packages, due to their low cost and low profile, are widely used in consumer electronics. Ni/Fe alloy (A42) is the most widely used leadframe material of SOT packages because of its low cost, good formability and CTE (coefficient of thermal expansion) match with silicon die. The very small size of SOT packages allow a higher package density on a board, but the small size and close proximity of SOT packages make thermal management difficult The low thermal conductivity of A42, which is less than one tenth of that of copper, makes the thermal conduction even more difficult Thus, the method of copper plating on A42 leadframe is used to enhance thermal conductivity of SOT packages while keeping their low cost and good CTE match between leadframe and silicon die. In this paper, the junction temperature Tj, the junction-to ambient thermal resistance 9j-a and the junction-to-solder joint thermal resistance 9j-sp were used to evaluate the heat dissipating ability of the package. The Finite Element Method was applied to study the influence of copper plating thickness on the thermal performance of a SOT package. Results show that with a thin layer of copper plating, the thermal resistance of the package can be greatly decreased. A thermal resistance circuit model and the corresponding thermal resistance expression on function of the copper plating thickness were then proposed to quantify the influence of copper plating thickness. The proposed expression, which follows a hyperbolic form, can well predict thermal resistance of the model.

Thermal and reliability analysis of clip bonding package using high thermal conductivity adhesive

“…Attentions have been drawn that package resistance is becoming the main contributor to the total product resistance instead of the intrinsic electrical silicon resistance [1,2]. The relationships between reliability and thermal resistance have been widely investigated [3][4][5], and it was demonstrated that a low thermal resistance can lead to high reliability [6]. Moreover, as the electronic packages are becoming smaller and thinner, there emerges an increasing demand for high signal integrity at high switch speeds.…”

Effects of Copper Plating Thickness of Ni/Fe Alloy Leadframe on Thermo-Mechanical and Die Cracking Behaviors of Small Outline Transistor (SOT) Packages

“…To quantify the influence of copper plating thickness on the thermal performance of SOT packages, a simplified thermal resistance circuit model is proposed and the corresponding mathematical expression of θ ja on function of copper plating thickness is deduced by fitting the model with simulation results using mean squares method [4]. Die cracking and die delamination caused by thermal residual stresses are common and critical issues for microelectronic packages.…”