No abstract

Small Outline Transistor (SOT) packages, due to their low cost and low profile, are widely used in consumer electronics. Ni/Fe alloy (A42) is the most widely used leadframe material of SOT packages because of its low cost, good formability and CTE (coefficient of thermal expansion) match with silicon die. The very small size of SOT packages allow a higher package density on a board, but the small size and close proximity of SOT packages make thermal management difficult The low thermal conductivity of A42, which is less than one tenth of that of copper, makes the thermal conduction even more difficult Thus, the method of copper plating on A42 leadframe is used to enhance thermal conductivity of SOT packages while keeping their low cost and good CTE match between leadframe and silicon die. In this paper, the junction temperature Tj, the junction-to ambient thermal resistance 9j-a and the junction-to-solder joint thermal resistance 9j-sp were used to evaluate the heat dissipating ability of the package. The Finite Element Method was applied to study the influence of copper plating thickness on the thermal performance of a SOT package. Results show that with a thin layer of copper plating, the thermal resistance of the package can be greatly decreased. A thermal resistance circuit model and the corresponding thermal resistance expression on function of the copper plating thickness were then proposed to quantify the influence of copper plating thickness. The proposed expression, which follows a hyperbolic form, can well predict thermal resistance of the model.

Small Outline Transistor (SOT) packages, widely used in consumer electronics, are very small, inexpensive surfacemount plastic molded packages. In order to maximize product throughput, the molded array matrix is employed for products fabrication, which leads to a potential critical wire sweep issue for SOT package during the transfer molding process. The unreasonably large wire sweep will extremely influence the package reliability, and even lead to failure of the product.

Small outline transistor (SOT) packages, because of their low cost and low profile, are widely used in consumer electronics. Ni/Fe alloy (A42) is the most widely used leadframe material of SOT packages because of its good formability and coefficient of thermal expansion (CTE) match with silicon die. The very small size of SOT packages allow a higher package density on a board, but the small size and close proximity of SOT packages make thermal management difficult. The low thermal conductivity of A42, which is less than one tenth of that of copper, makes the thermal conduction even more difficult. Thus, the method of copper plating on A42 leadframe is used to enhance the thermal conductivity of SOT packages while keeping their low cost and good CTE match between leadframe and silicon die. In this paper, the junction temperature T j , the junctionto-ambient thermal resistance θ j −a and the junction-to-solder joint thermal resistance θ j −sp are used to evaluate the heat dissipating ability of the package. The finite element method is applied to study the influence of copper plating thickness on the thermal performance of a SOT package. A thermal resistance circuit model and the corresponding thermal resistance expression on function of the copper plating thickness are then proposed to quantify the influence of copper plating thickness. The proposed expression, which follows a hyperbolic form, can well predict thermal resistance of the model. Finally, die cracking issue of the SOT packages with copper leadframe is examined and the residual stress on silicon die after die bonding process is studied. By comparing the cracking pattern and the stress state, shear fracture is proposed to be the crack initiation mechanism. Results also show that copper plating on A42 leadframe has little influence on the distribution of the thermal residual stress in the die. The stress level for the SOT package with copper plated A42 leadframe is much lower than that with copper leadframe, which makes the die cracking risk much lower.