Wire sweep study for SOT package array matrix molding with simulation and experimental analysis

Abstract

Small Outline Transistor (SOT) packages, widely used in consumer electronics, are very small, inexpensive surfacemount plastic molded packages. In order to maximize product throughput, the molded array matrix is employed for products fabrication, which leads to a potential critical wire sweep issue for SOT package during the transfer molding process. The unreasonably large wire sweep will extremely influence the package reliability, and even lead to failure of the product.

Improvement of pick & place yield in carrier tape packaging system through materials selection and cavity structure optimization

“…Small outline transistor (SOT) is a small surface mount transistor, commonly used in consumer electronics [2]. This kind of electronic devices is normally shipped by a carrier tape system.…”