Effects of Crystallographic Orientation on Mobility, Surface State Density, and Noise in p-Type Inversion Layers on Oxidized Silicon Surfaces

Sato, Taichiro; Takeishi, Y.; Hara, Hisashi

doi:10.1143/jjap.8.588

Cited by 126 publications

(49 citation statements)

References 13 publications

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“…Mobility on a (110) unstrained surface is found roughly 2.5 times higher than on a standard (001) wafer, in agreement with earlier measurements [36]. It was found that biaxial tensile stress decreases mobility on a (001) surface [15,16].…”

Section: Modeling Of P-channel Mosfetssupporting

confidence: 90%

Modeling of modern MOSFETs with strain

et al. 2009

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We review modeling techniques used to compute strain induced performance enhancement of modern MOSFETs. While p-channel MOSFETs were intensively studied, electron transport in strained structures received surprisingly little attention. A rigorous analysis of the subband structure in thin silicon films under stress is performed. Calculated subband effective masses are shown to strongly depend on shear strain and film thickness. A decrease of the transport effective mass under tensile stress in [110] direction and an additional splitting between the unprimed subbands with the same quantum number guarantees a mobility enhancement even in ultra-thin (001) silicon films. This increase of mobility and drive current combined with the improved channel control makes multi-gate MOSFETs based on thin films or silicon fins preeminent candidates for the 22 nm technology node and beyond.Keywords MOSFETs modeling · Shear strain · Two-band k·p model for conduction band · Valley splitting · Mobility and current enhancement

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Section: Modeling Of P-channel Mosfetssupporting

confidence: 90%

Modeling of modern MOSFETs with strain

et al. 2009

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“…3 However, the device performance and the uniformity can be improved further by control of the crystallographic orientation of the channel of the TFTs. It is well known that electronic properties of metal oxide semiconductor field effect transistors 4,5 ͑MOSFETs͒ have a pronounced dependence on the surface and in-plane crystal orientations with respect to the direction of the current flow due to the anisotropy of the effective mass. If the surface and even the in-plane orientations in the channel of the TFTs can be controlled in the location controlled grain, this grain will be ideal for c-Si TFT fabrication.…”

Section: Introductionmentioning

confidence: 99%

⟨100⟩-textured self-assembled square-shaped polycrystalline silicon grains by multiple shot excimer laser crystallization

Ishihara

Metselaar

et al. 2006

Journal of Applied Physics

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Strong preference for ͗100͘ surface and in-plane orientations has been observed in polycrystalline silicon film on SiO 2 after crystallization with multiple excimer laser pulses. Laser induced periodic surface structure ͑LIPSS͒ is developed in the film, constructing self-assembled square-shaped grains. The clear texture can be observed in a relatively wide energy density window, from 250 to 275 mJ/ cm 2 , for a 30 nm thick ␣-Si layer. It is speculated that the lateral growth velocity of ͗100͘-oriented grains is the fastest, and the orthogonal in-plane ͗100͘ directions are developed due to the alternate directions of melting and solidification during the LIPSS formation.

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“…This is typically accomplished by keeping transistors in northsouth orientation on the wafer, but by using a wafer with the crystal orientation rotated by 45 deg. The orientation of the surface normal (from channel to dielectric to electrode) also has an impact upon carrier mobility 50,51 . There is preferential surface orientation for both electrons and holes and it is not the same.…”

Section: Channel and Gate Engineeringmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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Effects of Crystallographic Orientation on Mobility, Surface State Density, and Noise in p-Type Inversion Layers on Oxidized Silicon Surfaces

Cited by 126 publications

References 13 publications

Modeling of modern MOSFETs with strain

Modeling of modern MOSFETs with strain

⟨100⟩-textured self-assembled square-shaped polycrystalline silicon grains by multiple shot excimer laser crystallization

Scaling Challenges for Advanced CMOS Devices

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