Effects of Different Solder Alloys on Reliability of 3D PLUS Solder Joint

Bao, Nuo; Wang, Chun Jie; Zhu, Lin; Song, Shun Guang

doi:10.4028/www.scientific.net/amr.314-316.1038

Cited by 3 publications

(6 citation statements)

References 7 publications

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“…Bao et al [142] used a nonlinear finite element analysis and plastic-ANAND model to evaluate the influences of Sn63pb37 tin-lead solder and Sn95.5Ag3.8Cu0.7 lead-free solder on the reliability of 3D-Plus memory solder joints. They calculated the stress-strain distribution and the potential failure locations of solder joints using a temperature cycling test.…”

Section: The Reliability Of Coc Package Memory Under Hygrothermal Stressmentioning

confidence: 99%

“…In [53,[141][142][143][144], the reliability research of PiP packaging is mainly carried out via a combination of finite element simulation and test verification, but the number of research topics classified as thermal stress and hygrothermal stress is relatively lower than those classified as PoP and CoC packaging. In addition, due to the internal encapsulation structure of PiP packaging devices and the absence of movable components, reliability research on mechanical stress is only carried out after assembly at board level.…”

Section: The Reliability Of Coc Package Memory Under Hygrothermal Stressmentioning

confidence: 99%

“…Such studies include analyzing the equivalent stress and plastic strain of printed board components of 3D-Plus memory under random vibrations and temperature cycling [141]. In terms of the reliability of solder joints subjected to thermal stress loads, the results of [142] show that there is a significant periodic change in the stress and plastic strain of solder joints, and the reliability of lead-free solder is greater than that of lead-based solder. The results of [143] show that thermal fatigue is the main cause of solder joint failure, and cracks are caused by the accumulation of plastic strain and creep strain.…”

Section: The Reliability Of Coc Package Memory Under Hygrothermal Stressmentioning

confidence: 99%

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Survey of Reliability Research on 3D Packaged Memory

Zhou

et al. 2023

Electronics

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As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.

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Section: The Reliability Of Coc Package Memory Under Hygrothermal Stressmentioning

confidence: 99%

Section: The Reliability Of Coc Package Memory Under Hygrothermal Stressmentioning

confidence: 99%

Section: The Reliability Of Coc Package Memory Under Hygrothermal Stressmentioning

confidence: 99%

See 1 more Smart Citation

Survey of Reliability Research on 3D Packaged Memory

Zhou

et al. 2023

Electronics

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show abstract

“…For example, Zhang et al [25] applied Anand material model to leader free solder joints to investigate inelastic deformation behavior of the leadfree solders. The parameters of Anand material model are shown in Table 3 [26].…”

Section: Analysis Process Of Soldering Residual Stressmentioning

confidence: 99%

Optimal Design of Co/In/Cu Sputtering Target Assembly Using Finite Element Method and Taguchi Method

Jiang

Zhang

Liu

2019

Acta Metall. Sin. (Engl. Lett.)

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Target assembly is a key consumable material for producing thin film used in the electronic packaging and devices. The residual stresses induced during the process of soldering are detrimental to the performance of target assembly. In this work, the intensity and distribution of the soldering residual stress of Co/In/Cu target assembly subjected to a 20 W/(m 2 K) cooling condition corresponding to the actual air cooling process were studied, based on finite element simulation and Taguchi method, to optimize the sputtering target assembly. Effects of different control factors, including solder material, thickness of solder layer, target and backing plate, on the soldering residual stress of target assembly are investigated. The maximum residual stress is calculated as 9.28 MPa in the target located at 0.16 mm from target-solder layer interface and at a distance of 0.78 mm from symmetry axis. The optimal design in target assembly has the combination of indium solder material, cobalt target at 12 mm thick, solder layer at 0.8 mm thick, copper backing plate at 15 mm thick. Moreover, solder material is the most important factor among control factors in the target assembly.

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“…Solder joints made with 96%Sn‐3.5%Ag‐0.5%Cu exhibit better electrical conductivity and mechanical strength compared with 63%Sn‐37%Pb joints . An emerging application of nanoscale SAC alloys is in metal‐based conductive inks (CIs) for printable electronics . These applications currently rely mainly on pure silver nanoparticle‐based inks, but inks based on lower cost materials are of great interest.…”

Section: Introductionmentioning

confidence: 99%

Flame synthesis of mixed tin‐silver‐copper nanopowders and conductive coatings

Sharma

Buchner

et al. 2015

AIChE Journal

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The single-step direct synthesis of tin-silver-copper nanopowders and nanostructured coatings using the flame-based high-temperature reducing jet (HTRJ) process is reported. Nanostructured coatings were deposited and sintered within the HTRJ reactor to study the effect of reductive sintering temperature on their electrical conductivity and surface morphology. Although the ultimate application of these nanoparticles is in printed electronics, which requires dispersing them as stable inks before depositing and sintering them, our approach of direct deposition from the gas phase provides an upper limit on the conductivity achievable with a given composition. The directly deposited coatings had high electrical conductivity, including a value of 2 3 10 6 S/m for 36 wt % Cu-40 wt % Ag-24 wt % Sn sintered at 2008C. This is twice the conductivity of a pure silver coating prepared under similar conditions. Moreover, similarly high electrical conductivity was achieved using only 20% Ag with sintering at 3008C. V C 2015 American Institute of Chemical Engineers AIChE J, 62: 408-414, 2016

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Effects of Different Solder Alloys on Reliability of 3D PLUS Solder Joint

Cited by 3 publications

References 7 publications

Survey of Reliability Research on 3D Packaged Memory

Survey of Reliability Research on 3D Packaged Memory

Optimal Design of Co/In/Cu Sputtering Target Assembly Using Finite Element Method and Taguchi Method

Flame synthesis of mixed tin‐silver‐copper nanopowders and conductive coatings

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