Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics

Shintri, Shashidhar; Yong, Chloe; Zhu, B.; Byrappa, Shayan; Fu, Bianzhu; Lo, Hsien-Ching; Choi, Dae Ro; Kolagunta, V.

doi:10.1016/j.mssp.2018.03.007

Cited by 11 publications

(4 citation statements)

References 11 publications

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“…For this application, in-line SIMS provides immediate feedback and speeds up the process development and epitaxial deposition tool recovery after preventative maintenance actions, for example. Different growth dynamics are expected for blanket film deposition compared to epitaxial growth within confined spaces such as source/drain epitaxy within the deep trenches of a nanosheet transistor structure [5]. Established in-line metrology solutions such as XPS or XRF typically do not have the necessary sensitivity and/or the high aspect ratios may limit their use to characterize the dopant profile in the source/drain material [1].…”

Section: Introductionmentioning

confidence: 99%

From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing

Schoeche,

Sieg,

Schmidt

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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This paper demonstrates the successful lab-to-fab transition of dynamic secondary-ion mass spectrometry (SIMS). In comparison to traditional lab SIMS, the in-line version is optimized for automated wafer and measurement sequence handling and high throughput measurements in small areas. Key advantages are fast turn-around time, reduced scrap, increased yield, and the measured wafer can continue processing in the manufacturing line. The benefits of in-line SIMS in the production environment are demonstrated for several use cases: matching and monitoring the long-term stability of epitaxy tools on monitor wafers, process optimization and monitoring of epitaxial Si and SiGe layers on blanket and patterned wafers with blanket metrology targets, measurement of implant and dopant profiles on blanket and patterned wafers, and characterization of the Ge and B diffusion in multi-layer stacks stimulated by high-temperature annealing. Additionally, the characterization of the source/drain epitaxy in a fully integrated nanosheet gate-all-around transistor architecture is demonstrated and discussed. The results are compared to off-line lab SIMS and alternative methods where available.

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Section: Introductionmentioning

confidence: 99%

From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing

Schoeche,

Sieg,

Schmidt

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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“…The material used in the S/D regions of p-type MOSFETs is typically boron doped Si1-xGex (4). The highest reported active doping concentration obtained through in-situ B doping is of the order 1×10 21 at./cm 3 for Ge concentrations between 40 and 70% (5).…”

Section: Introductionmentioning

confidence: 99%

“…The highest reported active doping concentration obtained through in-situ B doping is of the order 1×10 21 at./cm 3 for Ge concentrations between 40 and 70% (5). An excessive flow of B precursor during the deposition results in degraded epitaxial quality due to B segregation (4).…”

Section: Introductionmentioning

confidence: 99%

Low Temperature Epitaxy of In Situ GaDoped Si_1-XGe_x: Dopant Incorporation, Structural and Electrical Properties

Rengo¹,

Porret²,

Hikavyy³

et al. 2022

ECS Trans.

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The effect of the growth temperature and the Ga precursor flow on the epitaxy of Si1-xGex:Ga is studied. These parameters are found to have a significant impact on the Ga surface segregation behavior. In particular, Ga in situ doping impacts the growth rate of the epilayer, the Si1-xGex alloy composition, and the onset of strain relaxation. The growth temperature can be used to modulate the Ga segregation, enabling the deposition of materials with enhanced dopant concentrations and improved electrical properties. The Ga local atomic environment was studied in both a Si0.4Ge0.6:Ga and a Ge:Ga sample by X-ray absorption fine structure. The local environment of the Ga determined confirmed that the majority of dopants occupy a substitutional position within the lattice.

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“…Over the past decade, the chip industry has been following Moore's law to scale down transistors with FinFET technology [1][2][3][4][5][6][7]. A distinguishing characteristic of FinFET technology is that the gate wraps around the fin.…”

Section: Introductionmentioning

confidence: 99%

Performance boost using spacer-confined cavity for advanced FinFET technology

Peng

Zhan

et al. 2018

Semicond. Sci. Technol.

Self Cite

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We present a method to form a spacer-confined cavity to enable the deeper cavity for performance improvement while keeping the lateral width of epitaxial silicon doped with phosphorous (SiP EPI) from creating an EPI bridging issue. An extra non-selective etch step is introduced to leave the sidewall spacer but etch away the Si fin. The SiP EPI is confined between the sidewall spacer for EPI lateral width control. In this work, TCAD simulation shows that the effective gate length (L eff ) near the bottom of the fin decreases when cavity depth increases. The deeper junction provides another performance boost on top of the performance improvement from the fin height increase. In addition, the spacer-confined cavity demonstrates a 6% device performance improvement with comparable drain-induced-barrier-lowering at +8 nm cavity depth. The device performance starts saturation when the cavity depth extends beyond +15 nm. The spacer-confined cavity offers a solution to increase cavity depth without suffering from the EPI bridging issue for advance finFET technology.

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Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics

Cited by 11 publications

References 11 publications

From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing

From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing

Low Temperature Epitaxy of In Situ GaDoped Si_1-XGe_x: Dopant Incorporation, Structural and Electrical Properties

Performance boost using spacer-confined cavity for advanced FinFET technology

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Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics

Cited by 11 publications

References 11 publications

From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing

From lab to fab: in-line SIMS for process control in nanosheet gate-all-around device manufacturing

Low Temperature Epitaxy of In Situ GaDoped Si1-XGex: Dopant Incorporation, Structural and Electrical Properties

Performance boost using spacer-confined cavity for advanced FinFET technology

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Product

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Low Temperature Epitaxy of In Situ GaDoped Si_1-XGe_x: Dopant Incorporation, Structural and Electrical Properties