Effects of permanent and recoverable component of NBTI mechanisms on flip flop circuits designed using planar MOSFET and FinFET

Zainudin, M. F.; Hussin, H.; Halim, Abdul Karimi; Karim, Jamilah

doi:10.1109/iscaie.2018.8405460

Cited by 3 publications

(2 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…MOSRA is the built-in aging model integrated into Synopsys HSPICE, which can be used to predict the long-term reliability and performance of the circuit. Recently, MOSRA was deployed in many studies for reliability simulation and circuit design using the Synopsis HSPICE platform [17][18][19]. It should be noted that the MOSRA model itself is also constructed on the basis of a specific NBTI analytic model.…”

Section: Mosfet Model Reliability Analysis (Mosra) Aging Modelmentioning

confidence: 99%

“…Similarly to [23,24], our work also used the Nangate 45nm Open Cell Library, assuming 400 K and 10 years of operation during the experiment, and the simulation results of HSPICE were used to verify the accuracy and runtime performance. In [18,19], the aged delay of each circuit path in the designated 10th year was measured (corresponding tod xo 8 in this paper) and then compared with the HSPICE date (corresponding to the d xo 8 ). The obvious difference is that [23,24] calculated the aged path delay using the LUT method, while our proposed method was a machining learning framework at the circuit path level.…”

Section: Comparison With Other Studiesmentioning

confidence: 99%

See 1 more Smart Citation

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

2020

Electronics

View full text Add to dashboard Cite

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

show abstract

Section: Mosfet Model Reliability Analysis (Mosra) Aging Modelmentioning

confidence: 99%

Section: Comparison With Other Studiesmentioning

confidence: 99%