Effects of Si passivation on Ge metal-insulator-semiconductor interface properties and inversion-layer hole mobility

Abstract

The impact of Si passivation (SP) on Ge metal-insulator-semiconductor interface properties and the inversion-layer mobility of Ge p-type metal-insulator-semiconductor field effect transistors (PMISFETs) were investigated by using the devices with different thicknesses of the SP layers. SP was effective in decreasing the total charged centers instead of the interface traps. As a result, the inversion-layer hole mobility of the Ge MISFET was significantly improved by introducing the SP layers of the appropriate thickness. This improvement is attributable to the reduction of the amount of the interface charges and the separation of the positions of mobile carriers and the interface charges by the SP layers.

Effect of Ge passivation on interfacial properties of crystalline Gd2O3 thin films grown on Si substrates

“…It has been investigated quite extensively that an ultrathin Si layer serves as an effective passivation of Ge surfaces for deep sub micron Ge channel p-and n-FET application. [7][8][9] However, the effect of Ge on Si surface has not been investigated so far for CMOS application. It was reported recently that when a submonolayer of Ge deposited onto Si ͑111͒ surface, the center Si adatoms near the faulted half unit cell ͑FHUC͒ of a Si͑111͒-͑7 ϫ 7͒ unit cell transfer charges to the nearby Ge atoms and therefore making the dangling bond states of Si adatoms empty.…”

HfO2/GeO N /Ge gate stacks with sub-nanometer capacitance equivalent thickness and low interface trap density by in situ NH3 plasma pretreatment

“…Therefore, one of the most critical issues in Ge-based MOSFETs is the realization of gates stacks with superior MOS interfaces [4]. Fortunately, some methods to passivate the Ge interface have already been reported, such as the introduction of SiO 2 /Si [5], GeO 2 [6,7], GeO x N y [8,9], and rare earth oxides [10] as the interfacial control layer between Ge substrate and high-k layer. Although experimental and theoretical studies have proven good electrical properties of thermally grown GeO 2 /Ge interfaces, which exhibit a low D it of less than the mid 10 11 cm −2 eV −1 without any defect termination techniques [11][12][13].…”

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

“…100 The mobility variation can be explained by the charged centers in the gate oxide and strong remote Coulomb scattering due to defects at the Si/SiO 2 interface. 101 The fact that the increase in I on is inversely proportional to the EOT reveals the important scattering mechanisms due to defects located within the gate dielectric.…”