Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

Shi, Yi; Saitô, Kenichi; Ishikuro, Hiroki; Hiramoto, Toshiro

doi:10.1063/1.368346

Cited by 310 publications

(206 citation statements)

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“…This strongly suggests that the loss rate of stored electrons is directly related to the damage induced by irradiation at the Si-substrate/SiO 2 interface (Fig. 24c) as it was initially postulated by Shi (Shi et al, 1998). Previous measurements of electron loss at high temperatures revealed that the long-term retention of the present devices is due to the electron storage in NC traps (Dimitrakis & Normand, 2005).…”

Section: Effects On Charge Retentionsupporting

confidence: 48%

Radiation Hardness of Flash and Nanoparticle Memories

Verrelli¹,

Tsoukalas²

2011

Flash Memories

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Section: Effects On Charge Retentionsupporting

confidence: 48%

Radiation Hardness of Flash and Nanoparticle Memories

Verrelli¹,

Tsoukalas²

2011

Flash Memories

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“…Similar mechanism has been observed in silicon based metal-oxide-semiconductor memory where deep traps density in the floating gate governs the charge retention of the device. [20][21][22] In conclusion, OFET-based memory devices with different memory properties were demonstrated by controlling the Ag NPs layer thickness. The 1 nm Ag NP device shows a moderate memory window with 60 V and large on/off current ratio at about 10 5 .…”

Section: -2mentioning

confidence: 99%

Nonvolatile organic transistor-memory devices using various thicknesses of silver nanoparticle layers

Wang

Leung

Chan

2010

Applied Physics Letters

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We demonstrate the modification of the memory effect in organic memory devices by adjusting the thickness of silver nanoparticles ͑NPs͒ layer embedded into the organic semiconductor. The memory window widens with increasing Ag NPs layer thickness, a maximum window of 90 V is achieved for 5 nm Ag NPs and the on/off current ratio decreases from 10 5 to 10 when the Ag NPs layer thickness increases from 1 to 10 nm. We also compare the charge retention properties of the devices with different Ag NPs thicknesses. Our investigation presents a direct approach to optimize the performance of organic memory with the current structure. © 2010 American Institute of Physics. ͓doi:10.1063/1.3462949͔The advent of the nonvolatile flash memory has provided remarkable benefits for data storage in computers and other portable electronic devices. Due to the advantages of organic electronic devices over their inorganic counterparts such as the low fabrication costs, suitable for large area fabrication, and compatible with flexible substrates, 1,2 organic memory devices fabricated on flexible substrates have great potential for the next generation of nonvolatile flash memory. They can be further integrated with other electronic devices and form a flexible circuit. Recently a 26ϫ 26 array of organic flash memory transistors based on floating gate structure was demonstrated on flexible plastic sheets, and the operating voltage was as low as 6 V. 3 Currently, different approaches have been adopted to fabricate organic nonvolatile memory devices, such as using ferroelectric polymer dielectric materials 4,5 and chargeable gate dielectric in the organic field-effect transistors ͑OFETs͒. 6 In these devices, the memory effect arises from the field effect modulation by either the spontaneous polarization that occurs in ferroelectric, or through the trapping of charges in a chargeable layer of the dielectric. 7 Usually, the charge-trapping elements in the chargeable gate dielectric are nanoparticles ͑NPs͒ of metals such as Cr, 8 Au, 6 and Ag. 9 Compared with ferroelectric polymer-based memory, devices using metal NPs as charge traps have an advantage that the trap density and distribution can be controlled by adjusting the density and location of the NPs during the NP formation process, by using ultrathin metallic films deposition or ion implantation techniques. 10,11 Recently, we reported a different structure of transistor memory device with remarkable memory window performance by placing silver NPs in between two pentacene layers. 12 A significant advantage of the structure is that it can eliminate the extra fabrication steps for the insulator layers as in the case of floating gate transistor memory structure, making it suitable for integrating with other electronic devices on the same substrate to form a circuit. In the current work, we focused on investigating the performance variation in the pentacene OFET-based memory with different silver NP layer thickness. We also compared the memory window, on/off current ratio, and charge retention ...

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“…An interface trap is also useful to extend the current plateau in a single electron pump 4 at low temperatures, which is a promising candidate for a redefinition of ampere to establish a new current standard based on an elementary charge in quantum metrology. On the other hand, charge traps also affect reliability problems 5,6 , such as Random Telegraph Noise (RTN) 7-11 and Negative Bias Temperature Instabilities (NBTI) 12 , causing failures of Static Random Access Memory (SRAM) cells and degradations of long term performance 13,14 . In particular, the impact of RTN is getting more important with the scaling [15][16][17] , since the variations [18][19][20] in an atomic level can affect the drain current in sub-20 nm MOSFETs.…”

mentioning

confidence: 99%

Random-telegraph-noise by resonant tunnelling at low temperatures

Sotto

Liu

et al. 2017

2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

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The Random Telegraph Noise (RTN) in an advanced Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is considered to be triggered by just one electron or one hole, and its importance is recognised upon the aggressive scaling. However, the detailed nature of the charge trap remains to be investigated due to the difficulty to find out the exact device, which shows the RTN feature over statistical variations. Here, we show the RTN can be observed from virtually all devices at low temperatures, and provide a methodology to enable a systematic way to identify the bias conditions to observe the RTN. We found that the RTN was observed at the verge of the Coulomb blockade in the stability diagram of a parasitic Single-Hole-Transistor (SHT), and we have successfully identified the locations of the charge traps by measuring the bias dependence of the RTN.Charge traps in advanced Silicon (Si) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have been used for many important applications 1 in semiconductor industries. For example, a Metal-Oxide-NitrideOxide-Semiconductor (MONOS) memory device 2,3 has an advantage on a long retention time at high temperatures, which is suitable for an integrated microprocessor in a vehicle. An interface trap is also useful to extend the current plateau in a single electron pump 4 at low temperatures, which is a promising candidate for a redefinition of ampere to establish a new current standard based on an elementary charge in quantum metrology. On the other hand, charge traps also affect reliability problems 5,6 , such as Random Telegraph Noise (RTN) 7-11 and Negative Bias Temperature Instabilities (NBTI) 12 , causing failures of Static Random Access Memory (SRAM) cells and degradations of long term performance 13,14 . In particular, the impact of RTN is getting more important with the scaling [15][16][17] , since the variations [18][19][20] in an atomic level can affect the drain current in sub-20 nm MOSFETs. RTN is coming from the carrier trapping and de-trapping processes through charge traps at the gate insulator/Si interface, which are intrinsic quantum processes 21,22 . Quantum effects are not negligible in advanced MOSFETs, since the gate insulator is as thin as 1 nm 23 , and the direct tunnelling currents from the channel into the traps are expected due to enhanced coupling 24 . Previously, the most of the works on RTN were based on measurements at room temperatures [7][8][9][10][11]25,26 . At room temperatures, the thermal fluctuation significantly affect the carrier dynamics 27 , and it was difficult to identify the quantum energy levels of charge traps. By measuring the MOSFETs at low temperatures, it is easier to observe various quantum effects 28 . In our previous study, we have found current peaks at low temperatures in advanced Si MOSFETs 29 , but the mechanism of the peaks was not elucidated. In this paper, we characterised the peaks in time domain, and found that the current peaks are related to RTN. The bias conditions to observe the current peaks have b...

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Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

Cited by 310 publications

References 8 publications

Radiation Hardness of Flash and Nanoparticle Memories

Radiation Hardness of Flash and Nanoparticle Memories

Nonvolatile organic transistor-memory devices using various thicknesses of silver nanoparticle layers

Random-telegraph-noise by resonant tunnelling at low temperatures

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