Efficient algorithms for reconfiguration in VLSI/WSI arrays

Roychowdhury, Vwani P.; Bruck, Jehoshua; Kailath, T.

doi:10.1109/12.54841

Cited by 75 publications

(11 citation statements)

References 10 publications

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“…Although there is a large body of literature [2][3] [4][5] on the "un-ordered" escape routing problem, i.e., there is no constraint on the ordering of the escape pins, when it comes to ordered escape, not much research has been done. [6] and [7] have solved a related but different escape problem, where each pin has a fixed escape destination.…”

Section: Introductionmentioning

confidence: 99%

On using SAT to ordered escape problems

Luo

Wong

2009

2009 Asia and South Pacific Design Automation Conference

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Routing for high-speed boards is largely a timeconsuming manual task today. The ordered escape routing problem is one of the key problems in board-level routing, and Boolean Satisfiability (SAT) based approach [1] is the only solution to this problem so far. In this paper, we first solve the major deficiency of the original SAT formulation so that the escape problem is completely resolved. Then we propose two techniques to extend SAT approach for large-scale problems. Experimental results on industrial benchmarks show that our methods perform well in terms of both speed and routability.

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Section: Introductionmentioning

confidence: 99%

On using SAT to ordered escape problems

Luo

Wong

2009

2009 Asia and South Pacific Design Automation Conference

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“…There is a large body of literatures [1][2] [3][4] on the "unordered" escape routing problem, i.e., there is no constraint on the ordering of the escape pins. It is well known that the un-ordered problem can be solved optimally by a network flow approach.…”

Section: Introductionmentioning

confidence: 99%

Ordered escape routing based on Boolean satisfiability

Luo¹,

Wong²

2008

2008 Asia and South Pacific Design Automation Conference

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Abstract-Routing for high-speed boards is largely a timeconsuming manual task today. In this work we consider the ordered escape routing problem which is a key problem in boardlevel routing. All existing approaches to this problem cannot guarantee to find a routing solution even if one exists. We present an algorithm to exactly solve this problem based on Boolean satisfiability. Experimental results on escape routing problems from industry show that our algorithm performs well.

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“…We must note here that the above set of sufficient conditions are not necessary, I.e., a given array can be reconfigured even though a set of compensation paths meeting the above conditions cannot be found (see [6] for examples).…”

Section: Introductionmentioning

confidence: 97%

“…A polynomial time algorithm ( 0 ( l F l 2 ) , where IF1 is the number of faulty PES) for the same problem was presented in [6] and was later improved to an O(lF1 log IFI) time-complexity algorithm.…”

Section: Introductionmentioning

confidence: 97%

Reconfiguring processor arrays using multiple-track models

Varvarigou

Roychowdhury

Kailath

1991 Proceedings, International Conference on Wafer Scale Integration

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In this paper we present new results on systematic procedures for reconfiguring processor arrays in the presence of faulty processors. In particular, we consider models that use multiple tracks along every channel and a single spare row (or column) of Processing Elements (PES) along each boundary of the array. In the presence of faulty PES, the general methodology for reconfiguration involves replacing every faulty PE logically (rather than physically) by a spare PE through a sequence of logical substitutions; these sequences of substitutions are referred to as compensation paths. The determination of such compensation paths for every faulty PE has to be followed by an algorithm to connect each PE to its logical neighbors. It is easy to see that if the number of available routing tracks is fixed, then the compensation paths cannot be arbitrary. Hence, an important question to address is: how many tracks should one provide so as to allow a large enough class of compensation paths, and yet keep the hardware redundancy low. In this paper we show that if there exists a set of compensation paths subjected only to the constraints of continuity and nonintersection, then routing channels with three tracks are enough for the reconfiguration of the array. This theoretical result matches the empirical observations presented by several researchers showing that 3-track routing channels are sufficient for reconfiguring most instances. We refer to the underlying model as a 3-track-1-spare model; this is done to facilitate distinguish it from other models that not only use multiple tracks but also multiple spare rows (or columns) along each boundary. We present an efficient algorithm for reconfiguration in our 3-track-1-spare model and evaluate its performance. Our experimental results show that it has much higher reconfiguration probability than other models that use considerably more spare processors.

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Efficient algorithms for reconfiguration in VLSI/WSI arrays

Cited by 75 publications

References 10 publications

On using SAT to ordered escape problems

On using SAT to ordered escape problems

Ordered escape routing based on Boolean satisfiability

Reconfiguring processor arrays using multiple-track models

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