Efficient Analog Circuits for Boolean Satisfiability

Abstract

Abstract-Efficient solutions to NP-complete problems would significantly benefit both science and industry. However, such problems are intractable on digital computers based on the von Neumann architecture, thus creating the need for alternative solutions to tackle such problems. Recently, a deterministic, continuous-time dynamical system (CTDS) was proposed [1] to solve a representative NP-complete problem, Boolean Satisfiability (SAT). This solver shows polynomial analog time-complexity on even the hardest benchmark k-SAT (k ≥ 3) formulas, but at an energy cost through exponentially driven auxiliary variables. This paper presents a novel analog hardware SAT solver, AC-SAT, implementing the CTDS via incorporating novel, analog circuit design ideas. AC-SAT is intended to be used as a co-processor and is programmable for handling different problem specifications. It is especially effective for solving hard k-SAT problem instances that are challenging for algorithms running on digital machines. Furthermore, with its modular design, AC-SAT can readily be extended to solve larger size problems, while the size of the circuit grows linearly with the product of the number of variables and number of clauses. The circuit is designed and simulated based on a 32nm CMOS technology. SPICE simulation results show speedup factors of ∼10 4 on even the hardest 3-SAT problems, when compared with a state-of-the-art SAT solver on digital computers. As an example, for hard problems with N = 50 variables and M = 212 clauses, solutions are found within from a few ns to a few hundred ns.

Analog Approach to Constraint Satisfaction Enabled by Spin Orbit Torque Magnetic Tunnel Junctions

“…The power consumption of the total MTJ and heavy metal layer structures is approximately about 20% of the total power consumption of the system. Similarly, a recent work of a hardware realization 16 of an analog approach 8 , also explains that their overall power consumption to be significant (numerical value not specified), due to the usage of op-amps. In another design 15 , the CNN based SAT solving algorithm 9 used in our work was realized using op-amp based integrators.…”

“…However, implementing this set of analog formulae using a digital computer will diminish the polynomial time benefits, due to varying computational complexities between different time steps. Also, a hardware implementation of this analog k -SAT solver 8 is not ideal 16 , due to the exponential energy fluctuations in the system. Consequently, a Cellular Neural Network (CNN) based analog SAT solver with bounded variables was proposed 9 , and it is more appealing for hardware implementations.…”

A continuous-time MaxSAT solver with high analog performance

“…These numbers certainly depend on the digital hardware used. Note that in an analog circuit implementation, the current flow or voltage behavior would correspond to the equations of the solver, eliminating numerical integration issues and thus the algorithm should run much faster ( 46 shows a possible 10 4 speedup).…”

“…Instead of a numerical implementation on a digital computer, one would ideally like to use a direct implementation by analog circuits, the feasibility of which has been shown in ref. 46 , as it promises to be a faster (by orders of magnitude) and more efficient approach. One reason for this is that in such analog circuits the von Neumann bottleneck is eliminated, with the circuit itself serving its own processor and memory, see ref.…”

“…However, since one can control/generate energy much better than time itself, this presents a viable option for time-critical applications. 46 proposed an analog circuit design for the CTDS, showing a 10 4 -fold speedup on hard 3-SAT problems, when compared to state-of-the-art SAT solvers 47 , 48 on digital machines.…”