Efficient and Linear Power Amplifier Based on Envelope Elimination and Restoration

Vasić, Miroslav; García, O.; Oliver, J. A.; Alou, P.; Díaz, Daniel; Cobos, J.A.; Gimeno, Anthony; Pardo, José Manuel; Benavente, C. Marín; Ortega, Fernando

doi:10.1109/tpel.2011.2162005

Cited by 33 publications

(8 citation statements)

References 11 publications

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“…There are two reasons for the nonlinearity of the amplifier: one is the nonlinearity of the transistor itself; the other is that the amplifier does not work in the linear amplification region because of the improper setting of the DC operating point of the amplifier. The nonlinearity of transistor is closely related to its transconductance [28,29,30,31]. At low temperature, the transconductance of the device changes more sharply at different gate voltages than at room temperature.…”

Section: Post Simulation Resultsmentioning

confidence: 99%

A cryogenic low power CMOS analog buffer at 4.2K

Huang

Luo

et al. 2021

IEICE Electron. Express

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A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit achieves a slew-rate of +36 V/µs and -33.8 V/µs for 10 pF capacitive load. The static power of the circuit is only 55.7µW.

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Section: Post Simulation Resultsmentioning

confidence: 99%

A cryogenic low power CMOS analog buffer at 4.2K

Huang

Luo

et al. 2021

IEICE Electron. Express

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“…In order to increase back-off efficiency, various techniques have been proposed, both at the PA and at the system level, such as the Doherty power amplifier [13,15] and the Chireix outphasing [16,17] PA, based on the load modulation concept [18], or Envelope Elimination and Restoration (EER) [19,20] and Envelope Tracking (ET) [21,22] techniques, based instead on supply modulation. A combination of both supply and load modulation can be also exploited to maximize the achievable back-off efficiency [23,24].…”

Section: Introductionmentioning

confidence: 99%

Design of a Wideband Doherty Power Amplifier with High Efficiency for 5G Application

et al. 2021

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This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

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“…Traditional linearization methods, include resistor degeneration and resistor feedback, are simple, but will reduce the gain and worsen the noise figure and bandwidth. Linearization techniques for power amplifiers (PAs) have been proposed [2]- [10], but the complexity and power consumption in PA linearization limit their application in the LNA design.…”

Section: Introductionmentioning

confidence: 99%

Linearization of Bipolar Amplifiers Based on Neural-Network Training Algorithm

Kolbusz

Wilamowski

2016

IEEE Trans. Ind. Electron.

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Traditional bipolar differential amplifiers have only a ±5mV operational range with nonlinear distortion below 0.1dB. In this paper, a linearization technique based on neural network training algorithm is proposed to expand this 0.1dB linear region to a much wider ±200mV range. Compared with the traditional and recent state-of-the-art techniques for linearization, where gain or noise performance is always being tradeoff for high linearity, the proposed technique leads to the increase of the amplifier's gain with low noise. Another advantage of the proposed approach is that, it is implemented using a simple, paralleled structure that leads to a smaller area and less power consumption than other linearization schemes. The design procedure also enables a completely customizable solution based on required linear range, ripples, and the number of available transistors. The experimental results show that the proposed linearized amplifier has a very good linearity and is capable to wide bandwidth, good gain, and low noise performance.

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Efficient and Linear Power Amplifier Based on Envelope Elimination and Restoration

Cited by 33 publications

References 11 publications

A cryogenic low power CMOS analog buffer at 4.2K

A cryogenic low power CMOS analog buffer at 4.2K

Design of a Wideband Doherty Power Amplifier with High Efficiency for 5G Application

Linearization of Bipolar Amplifiers Based on Neural-Network Training Algorithm

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