Efficient application representation for HASTE: Hybrid Architectures with a Single, Transformable Executable

Levine, B.; Schmit, Herman

doi:10.1109/fpga.2003.1227246

Cited by 21 publications

(12 citation statements)

References 11 publications

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“…Several projects such as PipeRench [6] and HASTE [7] have investigated the mapping of execution kernels into coarse-grained reconfigurable fabrics utilizing arithmetic and logic units (ALUs). The RaPid project [8] presents another coarse-grain, pipelined, configurable architecture.…”

Section: Related Workmentioning

confidence: 99%

Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions

Ihrig

Stander

Jones

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Section: Related Workmentioning

confidence: 99%

Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions

Ihrig

Stander

Jones

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…While our technique applies to stripe-based reconfigurable fabrics in general such as PipeRench ( [13,14]) and Kilocore ( [4]), and conceptually to the larger class of coarse-grained reconfigurable fabrics, our technique is demonstrated using the low-energy domain specific fabric (DSF) target ( [5]) shown in Figure 2.…”

Section: Figure 1: Comparison Of Alus Used For Routing and Computationmentioning

confidence: 99%

“…RaPiD (Reconfigurable Pipelined Datapath) [7,15], mainly intended for computation-intensive applications, consists of a linear array of application-specific functional units. PipeRench [13,14], Kilocore ( [4]) have a striped configuration and is comprised of an interconnected network of configurable logic blocks and storage elements. It consists of a set of physical pipeline stages called stripes and each stripe contains a set of processing elements, register files, and an interconnec-tion network.…”

Section: Background and Literature Reviewmentioning

confidence: 99%

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Yadav

Stander

Jones

et al. 2013

VLSICS

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Coarse-grained reconfigurable fabrics (CGRF's) have great promise for achieving low-energy flexible designs for an application domain. However a universally accepted architecture for coarse-grained reconfigurable fabrics has not yet crystallized, and many architectural options are still un-der consideration by the research and industry community. One scientific question is how to efficiently route inputs through a CGRF. This paper addresses this question in part by exploring various alternative input solu-tions for a stripe-based fabric. Alternative architectural styles examined in this paper include (i) integrated constants (IC) approach where constants are loaded in the registers local to the functional units; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routed to the stripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) a combination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles.We implemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailed area and energy analysis on these architectures and present quantitative results in this paper. We observed that the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and 62% area savings over a baseline architecture for our benchmark set.

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“…Stitt and Vahid [16,17] reported work on hardware-software partitioning of software binaries. Levine and Schmidt [10] proposed a hybrid architecture called HASTE, in which instructions from an embedded processor are dynamically compiled onto a reconfigurable computational fabric using a hardware compilation unit. Ye et al [18] developed a similar compiler system for the CHIMAERA architecture.…”

Section: Related Workmentioning

confidence: 99%

Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code

Zaretsky

Mittal

Dick

et al. 2006

Languages and Compilers for Parallel Computing

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Abstract. High-level synthesis tools generally convert abstract designs described in a high-level language into a control and data flow graph (CDFG), which is then optimized and mapped to hardware. However, there has been little work on generating CDFGs from highly pipelined software binaries, which complicate the problem of determining data flow propagation and dependencies. This paper presents a methodology for generating CDFGs from highly pipelined and scheduled assembly code that correctly represents the data dependencies and propagation of data through the program control flow. This process consists of three stages: generating a control flow graph, linearizing the assembly code, and generating the data flow graph. The proposed methodology was implemented in the FREEDOM compiler and tested on 8 highly pipelined software binaries. Results indicate that data dependencies were correctly identified in the designs, allowing the compiler to perform complex optimizations to reduce clock cycles.

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Efficient application representation for HASTE: Hybrid Architectures with a Single, Transformable Executable

Abstract: Abstract

Cited by 21 publications

References 11 publications

Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions

Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code

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