Reconfigurable computing will change the way computing systems are designed, built, and used. PipeRench, a new reconfigurable fabric, combines the flexibility of general-purpose processors with the efficiency of customized hardware to achieve extreme performance speedup.

Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.

the more general case in which the iniinsight and techniques that apply to 0thtial functional specification may consist er forms of hardwaresoftware codesign for Hardware-Software theoretical work aimed at identifying factors that influence design decisions with IN HARDWARE-SOWARE code sign, designers consider trade-offs in the way hardware and software components of a system work to gether to exhibit a specified behavior, given aset of performance goals and an implementation technolo gy. Because of a wide range of possible system structures and design goals, the hardwaresoftware codesign problem takes on many forms.One type of codesign seeks to accelerate application software by extmcting portions for implementation in hardware. Programmable hardware may make this type of software acceleration common even in genemlpulpose computing. In thls case, the codesign problem entails characterizing hardware and software performance, identifying a hardware software partition, transforming the functional description intosuch a partition, and synthesizing the resulting hardware and software.

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While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualizationcan be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be acheived using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility.Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per-mm*.