Managing pipeline-reconfigurable FPGAs

Abstract

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualizationcan be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be acheived using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility.Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per-mm*.

Compiler Optimizations for Adaptive EPIC Processors

“…Other notable reconfigurable computing projects include the Programmable Reduced Instruction Set Computer (prisc) [21,22], garp [16], disc [31], rapid [13], the CMU Cached Virtual Hardware (cvh), PipeRench [5], and Chimaera [14,15].…”

A reconfigurable arithmetic array for multimedia applications

“…But these architectures do not exploit the clustering to reduce the configuration memory overhead, presumably because doing so would compromise their ability to support general-purpose logic. A number of academic architectures [3,4,5,6,7,8,11] (discussed in Section 7) have recognised this issue and concentrate on denser support for arithmetic applications even at the expense of generality. These architectures are based on one or both of two major techniques: the sharing of configuration bits between multiple bits of word width and the use of function blocks tuned for arithmetic applications.…”

“…In contrast, CHESS shares one routing structure between data and carry/control connections 4 . This means that CHESS uses only 1 wire in a 4-bit bus used for a carry/control connection, but we prefer that to incurring the overhead of a separate control network.…”

Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

“…PipeRench [30] reconfigures the hardware every cycle to overcome the limitation of hardware resources.…”

“…In our example, each stage is implemented by an 8-bit constant coefficient multiplier and a 24-bit adder to accumulate up to 256 taps in Figure 6.1(a). The input data is double pipelined in one stage for the appropriate computation [30]. An 8x8 constant coefficient multiplier can be implemented using two 4x8 constant coefficient multipliers and a 12-bit adder with, appropriate connections [54].…”