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Abstract

Abstract| Error correcting codes ECCs are widely used in digital communications. Recently, new types of ECCs have been proposed which permit error-free data transmission over noisy channels at rates which approach the Shannon capacity. For wireless communication, these new codes allow more data to be carried in the same spectrum, lower transmission power, and higher data security and compression. One new type of ECC, referred to as Turbo Codes," has received a lot of attention, but is computationally expensive to decode and di cult to realize in hardware. Low Density Parity Check Codes LDPCs, another ECC, also provide near Shannon limit error correction ability. However, LDPCs use a decoding scheme which is much more amenable to hardware implementation. This paper will rst present an overview of these coding schemes, then discuss the issues involved in building an LDPC decoder using recon gurable hardware. We present a hypothetical LDPC implementation using a commercial FPGA, which will give an idea of future research issues and performance gains.

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