Implementation of near Shannon limit error-correcting codes using reconfigurable hardware

Abstract

Abstract| Error correcting codes ECCs are widely used in digital communications. Recently, new types of ECCs have been proposed which permit error-free data transmission over noisy channels at rates which approach the Shannon capacity. For wireless communication, these new codes allow more data to be carried in the same spectrum, lower transmission power, and higher data security and compression. One new type of ECC, referred to as Turbo Codes," has received a lot of attention, but is computationally expensive to decode and di cult to realize in hardware. Low Density Parity Check Codes LDPCs, another ECC, also provide near Shannon limit error correction ability. However, LDPCs use a decoding scheme which is much more amenable to hardware implementation. This paper will rst present an overview of these coding schemes, then discuss the issues involved in building an LDPC decoder using recon gurable hardware. We present a hypothetical LDPC implementation using a commercial FPGA, which will give an idea of future research issues and performance gains.

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“…We also discarded LDPC codes [25], which are very efficient but require very large and sparse binary matrices, thus making them resource intensive in hardware applications (see e.g. [26,27] for designs targeting FPGAs, which occupy more than 50% of a high-end FPGA). We do not consider Hadamard codes explicitly but notice that they are equivalent to first-order ReedMuller codes.…”

Low-Density Parity-Check Codes and Their Rateless Relatives

“…Hence it is desirable that the LDPC construction can be conveniently implemented in hardware. Several LDPC hardware implementations have been proposed, for example in [176]- [183], with many of them exploiting the speed and flexibility of field programmable gate arrays (FPGA) and of digital signal processors.…”

An improved implementation of sum-product algorithm for LDPC decoder

“…And the proposed method presents low computational complexity and simple structure for implementation. Moreover, the computational complexity of proposed method is almost unchanged as the number of the expansion points increases, which is suitable for ASIC or FPGA implementation [9]. Furthermore, this design can also be applied to LDPC codes over GF(q) [10].…”