Efficient crosstalk estimation

Kuhlmann, M.; Sapatnekar, Sachin S.; Parhi, K.K.

doi:10.1109/iccd.1999.808435

Cited by 38 publications

(18 citation statements)

References 14 publications

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“…(15), δv peak /δC C is positive but diminishes when t v >> t r in which case reduction in coupling capacitance doesn't help peak noise reduction. Eqn's (16,17,18,19,20,21) show that an increase in the ground caps of both victim and aggressor lines help reduce noise on the victim net. Their relative effectiveness's are as follows.…”

Section: Noise Avoidance Techniquementioning

confidence: 99%

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Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Hunagund¹,

Kalpana²

2011

IJET

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Abstract-Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 3GHz has caused crosstalk noise to become a serious problem that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width to estimate on-chip crosstalk noise and also shown that crosstalk can be minimized by wire spacing and wire sizing optimization technique. These models are verified for various deep submicron technologies.Index Terms-Aggressor, Coupling, Crosstalk, Interconnect noise, Wire spacing, I. INTRODUCTIONAdvancement in the field of very large scale integration (VLSI) have lead to a decrease in device geometries (deep submicron technology), high device densities, high clock rates, and thus small signal transition times. Thus, interconnection lines that were once considered to be electrically isolated can now interfere with each other and have an important impact on system performance and correctness. One such interaction caused by parasitic coupling between wires is known as crosstalk. If not carefully considered during design validation, crosstalk can cause extra signal delay, logic hazards, and even circuit malfunction. Accurate modeling and simulation of interconnect delay due to crosstalk thus becomes increasingly important in the design of high-performance integrated circuits.The net on which noise is being induced is called the victim net whereas the net that induces this noise is called the aggressor net. Crosstalk noise not only leads to modified delays [2], [ 3] but also to potential logic malfunctions [4], [ 5]. To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages. Any such tool requires fast yet accurate crosstalk noise models both to estimate noise and also to see the effects of Manuscript received September 19, 2011; revised December 3, 2011. P. V. Hunagund is with the Department of Applied Electronics, Gulbarga University, Gulbarga, India (e-mail:prabhakar.hunagund@gmail.com).A. B. Kalpana is with the Electronics and Communication Engineering Department, Bangalore Institute of Technology, Bangalore, India (e-mail: abkalpana@gmail.com).various interconnect and driver parameters on noise. Several papers, which propose crosstalk models, can be found in recent literature. In [6], telegraph equations are solved directly to find a set of analytical formulae for peak noise in capacitively coupled bus lines. [7] derives bounds for crosstalk noise using a lumpe...

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Section: Noise Avoidance Techniquementioning

confidence: 99%

“…As a result, when a victim wire's width is increased, the change in peak noise depends on Eqn's (16,17,18,25,26). Eqn's (25 and 26) show the importance of coupling location on how effective wire sizing will be.…”

Section: B Wire Sizingmentioning

confidence: 99%

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Hunagund¹,

Kalpana²

2011

IJET

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show abstract

“…After a brief description of Devgan's metric in Section 2.1, we introduce our new noise metric in Section 2.2. We next compare our metric with the analytical models proposed by Vittal [10], Devgan [11], and Kuhlmann [12], [14] through a series of detailed simulation experiments. Finally, Section 3 provides the conclusion of this paper.…”

Section: Introductionmentioning

confidence: 99%

“…Authors demonstrate the accuracy of their proposed method by comparing its performance with that of HSPICE. The metric proposed in [12] and [14] is less intuitive in terms of the circuit interpretation, and requires two tree traversals (one for the aggressor net and the other one for the victim net), a diagonal matrix-vector multiplication for the DC component of the Taylor series expansion of the victim voltage in the Laplacedomain, two additional tree traversals per moment, and two diagonal matrix-vector multiplication for high moments of the victim and the aggressor voltages. The tree traversal and the multiplication are of the order of O(n) for n nodes.…”

Section: Introductionmentioning

confidence: 99%